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Searched refs:mmWD_UTCL1_CNTL (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c	`553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`300 #define mmWD_UTCL1_CNTL 0x0243`
gc_9_1_offset.h	`296 #define mmWD_UTCL1_CNTL 0x0243`
gc_9_2_1_offset.h	`290 #define mmWD_UTCL1_CNTL 0x0243`
gc_10_1_0_offset.h	`2308 #define mmWD_UTCL1_CNTL 0x0fe3 [all...]`

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