| /src/sys/arch/arm/rockchip/ |
| rk_cru_pll.c | 185 if (__SHIFTOUT(CRU_READ(sc, pll->mode_reg), pll->mode_mask) ==
187 CRU_WRITE(sc, pll->mode_reg,
230 CRU_WRITE(sc, pll->mode_reg,
254 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
|
| rk3399_pmucru.c | 249 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
276 .u.pll.mode_reg = (_mode_reg), \
291 PLL_CON(3), /* mode_reg */
|
| rk_cru.h | 95 bus_size_t mode_reg; member in struct:rk_cru_pll
120 .u.pll.mode_reg = (_mode_reg), \
|
| rk3399_cru.c | 349 .u.pll.mode_reg = (_mode_reg), \
398 PLL_CON(3), /* mode_reg */
404 PLL_CON(11), /* mode_reg */
410 PLL_CON(19), /* mode_reg */
416 PLL_CON(27), /* mode_reg */
422 PLL_CON(35), /* mode_reg */
428 PLL_CON(43), /* mode_reg */
434 PLL_CON(51), /* mode_reg */
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_cursor.c | 47 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
|
| nouveau_dispnv04_tvnv04.c | 84 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
112 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
151 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
|
| nouveau_dispnv04_dfp.c | 100 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
127 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
142 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
211 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
255 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
292 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
468 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
559 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
560 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
562 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk)
[all...] |
| disp.h | 82 struct nv04_mode_state mode_reg; member in struct:nv04_display
|
| nouveau_dispnv04_crtc.c | 67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
658 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
668 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
730 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
775 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
786 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
[all...] |
| hw.h | 378 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
|
| nouveau_dispnv04_tvnv17.c | 408 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
469 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
|
| nouveau_dispnv04_tvmodesnv17.c | 552 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
|
