/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
amdgpu_dcn10_mpc.c | 47 int mpcc_id) 50 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); 66 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, 68 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, 70 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, 77 int mpcc_id) 80 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); 82 REG_UPDATE_5(MPCC_CONTROL[mpcc_id], 89 mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); 96 int mpcc_id) 283 int mpcc_id = mpcc_to_remove->mpcc_id; local in function:mpc1_remove_mpcc 361 int mpcc_id; local in function:mpc1_mpc_init 407 int mpcc_id; local in function:mpc1_init_mpcc_list_from_hw [all...] |
dcn10_mpc.h | 144 int mpcc_id); 156 unsigned int mpcc_id); 170 int mpcc_id); 174 int mpcc_id); 178 int mpcc_id); 186 int mpcc_id);
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amdgpu_dcn10_hw_sequencer.c | 1216 hubp->mpcc_id = dpp->inst; 2142 int mpcc_id; local in function:dcn10_update_mpcc 2188 mpcc_id = hubp->inst; 2192 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2197 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2204 dc->res_pool->mpc, mpcc_id); 2213 mpcc_id); 2218 hubp->mpcc_id = mpcc_id;
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amdgpu_dcn10_hubp.c | 70 hubp->mpcc_id = 0xf; 1280 hubp1->base.mpcc_id = 0xf;
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
amdgpu_dcn20_mpc.c | 56 int mpcc_id) 60 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); 62 REG_UPDATE_7(MPCC_CONTROL[mpcc_id], 71 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); 72 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); 73 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); 75 mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id); 279 struct mpc *mpc, int mpcc_id, 284 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, 290 struct mpc *mpc, int mpcc_id, [all...] |
dcn20_mpc.h | 281 int mpcc_id); 307 int mpcc_id, 311 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id); 312 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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amdgpu_dcn20_hwseq.c | 720 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local in function:dcn20_program_output_csc 723 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 743 int mpcc_id = pipe_ctx->plane_res.hubp->inst; local in function:dcn20_set_output_transfer_func 754 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 774 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 2144 int mpcc_id; local in function:dcn20_update_mpcc 2189 mpcc_id = hubp->inst; 2192 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2199 dc->res_pool->mpc, mpcc_id); 2208 mpcc_id); [all...] |
amdgpu_dcn20_hubp.c | 938 hubp->mpcc_id = 0xf; 1604 hubp2->base.mpcc_id = 0xf;
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
mpc.h | 105 int mpcc_id; /* MPCC physical instance */ member in struct:mpcc 159 * [in] mpcc_id - The MPCC physical instance to use for blending. 170 int mpcc_id); 198 unsigned int mpcc_id); 206 * [in] mpcc_id - The MPCC physical instance. 213 int mpcc_id); 221 void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); 248 int mpcc_id, 252 int mpcc_id,
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hubp.h | 63 int mpcc_id; member in struct:hubp
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
amdgpu_dcn21_hubp.c | 962 hubp21->base.mpcc_id = 0xf;
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