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    Searched refs:mpcc_inst (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_mpc.c 339 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
341 mpcc->mpcc_id = mpcc_inst;
445 int mpcc_inst,
450 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
451 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
452 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
453 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
457 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
dcn10_mpc.h 194 int mpcc_inst,
amdgpu_dcn10_hw_sequencer.c 1049 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1215 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1222 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2835 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2840 if (res_pool->hubps[i]->inst == mpcc_inst)
2853 int mpcc_inst; local
2862 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2863 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
    [all...]
amdgpu_dcn10_resource.c 1157 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
mpc.h 144 int mpcc_inst,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dmub_psr.c 144 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_cmd.h 223 uint8_t mpcc_inst; member in struct:dmub_cmd_psr_copy_settings_data
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 254 uint8_t mpcc_inst; member in struct:plane_resource
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 1239 && old_pipe->bottom_pipe->plane_res.mpcc_inst
1240 != new_pipe->bottom_pipe->plane_res.mpcc_inst))
1370 int mpcc_inst = hubp->inst; local
1375 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1376 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1377 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
2361 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2371 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
amdgpu_dcn20_mpc.c 518 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
520 mpcc->mpcc_id = mpcc_inst;
amdgpu_dcn20_resource.c 1742 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1817 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
3005 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 1249 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1654 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
1926 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
1932 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
1935 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
1938 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 530 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;

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