| /src/sys/arch/powerpc/ibm4xx/dev/ |
| mal.c | 85 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR);
110 mtdcr(DCR_MAL0_CFG,
120 mtdcr(DCR_MAL0_CFG,
128 mtdcr(DCR_MAL0_IER,
148 mtdcr(DCR_MAL0_TXEOBISR, MAL0__XCAR_CHAN(chan));
165 mtdcr(DCR_MAL0_RXEOBISR, MAL0__XCAR_CHAN(chan));
185 mtdcr(DCR_MAL0_TXDEIR, MAL0__XCAR_CHAN(chan));
203 mtdcr(DCR_MAL0_RXDEIR, MAL0__XCAR_CHAN(chan));
206 mtdcr(DCR_MAL0_RXCASR, MAL0__XCAR_CHAN(chan));
223 mtdcr(DCR_MAL0_ESR, esr)
[all...] |
| exb.c | 78 /* mtdcr needs a constant */
80 case 0: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B0CR); break;
81 case 1: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B1CR); break;
82 case 2: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B2CR); break;
83 case 3: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B3CR); break;
84 case 4: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B4CR); break;
85 case 5: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B5CR); break;
86 case 6: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B6CR); break;
87 case 7: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B7CR); break;
|
| ecc_plb.c | 149 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
152 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR);
157 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
158 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff);
231 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
234 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
235 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff);
269 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
|
| /src/sys/arch/powerpc/ibm4xx/ |
| ibm4xx_460ex_l2.c | 86 mtdcr(DCR_L2C0_ADDR, 0);
87 mtdcr(DCR_L2C0_CMD, L2C_CMD_HCC);
116 mtdcr(DCR_L2C0_ADDR, ibm4xx_460ex_l2_addr(addr));
117 mtdcr(DCR_L2C0_CMD, L2C_CMD_INV);
173 mtdcr(DCR_SRAM0_SB0CR, 0);
174 mtdcr(DCR_SRAM0_SB1CR, 0);
175 mtdcr(DCR_SRAM0_SB2CR, 0);
176 mtdcr(DCR_SRAM0_SB3CR, 0);
179 mtdcr(DCR_L2C0_CFG, L2C_CFG_RDBW | L2C_CFG_L2M | L2C_CFG_SS_256KB);
182 mtdcr(DCR_L2C0_ADDR, 0)
[all...] |
| pic_uic.c | 80 * cleared by mtdcr, no matter whether sync (= eieio) and/or
117 mtdcr(DCR_EXISR, v);
123 mtdcr(DCR_EXIER, v);
170 mtdcr(DCR_UIC0_BASE + DCR_UIC_SR, v);
176 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, v);
228 mtdcr(DCR_UIC1_BASE + DCR_UIC_SR, v);
234 mtdcr(DCR_UIC1_BASE + DCR_UIC_ER, v);
282 mtdcr(DCR_UIC2_BASE + DCR_UIC_SR, v);
288 mtdcr(DCR_UIC2_BASE + DCR_UIC_ER, v);
338 mtdcr(DCR_UIC3_BASE + DCR_UIC_SR, v)
[all...] |
| /src/sys/arch/powerpc/include/ibm4xx/ |
| cpu.h | 94 mtdcr(const int reg, uint32_t val) function
96 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val));
111 mtdcr(DCR_CPR0_CFGADDR, reg);
112 mtdcr(DCR_CPR0_CFGDATA, val);
118 mtdcr(DCR_CPR0_CFGADDR, reg);
125 mtdcr(DCR_SDR0_CFGADDR, reg);
126 mtdcr(DCR_SDR0_CFGDATA, val);
132 mtdcr(DCR_SDR0_CFGADDR, reg);
|
| /src/sys/arch/evbppc/sam460ex/ |
| autoconf.c | 110 mtdcr(DCR_UIC1_BASE + DCR_UIC_PR,
112 mtdcr(DCR_UIC1_BASE + DCR_UIC_TR,
114 mtdcr(DCR_UIC1_BASE + DCR_UIC_SR, 0x80000000);
115 mtdcr(DCR_UIC3_BASE + DCR_UIC_PR,
117 mtdcr(DCR_UIC3_BASE + DCR_UIC_TR,
119 mtdcr(DCR_UIC3_BASE + DCR_UIC_SR, 0x000ff000);
|
| machdep.c | 222 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
223 mtdcr(DCR_UIC1_BASE + DCR_UIC_ER, 0);
224 mtdcr(DCR_UIC2_BASE + DCR_UIC_ER, 0);
225 mtdcr(DCR_UIC3_BASE + DCR_UIC_ER, 0);
|
| /src/sys/arch/evbppc/obs405/ |
| obs200_autoconf.c | 58 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
|
| obs266_autoconf.c | 58 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
|
| obs200_locore.S | 143 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
144 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM. Just in case */
|
| obs600_autoconf.c | 103 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
|
| obs200_machdep.c | 129 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
|
| /src/sys/arch/powerpc/ibm4xx/pci/ |
| pciex.c | 280 * mtdcr() needs compile-time constant DCR numbers.
284 mtdcr((base) + PEGPL_CFGMSK, 0); \
285 mtdcr((base) + PEGPL_CFGBAH, AMCC460EX_PCIE_CFG_PA_HIGH); \
286 mtdcr((base) + PEGPL_CFGBAL, (cfg_plba)); \
287 mtdcr((base) + PEGPL_CFGMSK, \
289 mtdcr((base) + PEGPL_OMR1BAH, AMCC460EX_PCIE_MEM_PA_HIGH); \
290 mtdcr((base) + PEGPL_OMR1BAL, (mem_plba)); \
291 mtdcr((base) + PEGPL_OMR1MSKH, 0x7fffffff); \
292 mtdcr((base) + PEGPL_OMR1MSKL, \
295 mtdcr((base) + PEGPL_CFG,
[all...] |
| /src/sys/arch/evbppc/dht/ |
| autoconf.c | 66 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
|
| locore.S | 133 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
134 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM.
|
| machdep.c | 147 mtdcr(DCR_SDRAM0_CFGADDR, addr);
169 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
|
| /src/sys/arch/evbppc/virtex/ |
| dcr.h | 78 case (addr): mtdcr((base) + (addr) / 4, val); break
|
| idcr.h | 79 #define mtidcr(addr, val) mtdcr(IDCR_BASE + (addr), (val))
|
| virtex_start.S | 121 mtdcr DCR_OCM0_DSCNTL,%r0 /* Disable Data access to OCM */
|
| /src/sys/arch/evbppc/walnut/ |
| autoconf.c | 69 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
|
| machdep.c | 107 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
|
| /src/sys/arch/powerpc/ibm4xx/openbios/ |
| locore.S | 142 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
143 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM. Just in case */
|
| /src/sys/arch/evbppc/explora/ |
| machdep.c | 103 mtdcr(DCR_EXIER, 0);
|
