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    Searched refs:mtdcr (Results 1 - 20 of 20) sorted by relevancy

  /src/sys/arch/powerpc/ibm4xx/dev/
mal.c 84 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR);
109 mtdcr(DCR_MAL0_CFG,
119 mtdcr(DCR_MAL0_CFG,
127 mtdcr(DCR_MAL0_IER,
147 mtdcr(DCR_MAL0_TXEOBISR, MAL0__XCAR_CHAN(chan));
164 mtdcr(DCR_MAL0_RXEOBISR, MAL0__XCAR_CHAN(chan));
184 mtdcr(DCR_MAL0_TXDEIR, MAL0__XCAR_CHAN(chan));
202 mtdcr(DCR_MAL0_RXDEIR, MAL0__XCAR_CHAN(chan));
205 mtdcr(DCR_MAL0_RXCASR, MAL0__XCAR_CHAN(chan));
222 mtdcr(DCR_MAL0_ESR, esr)
    [all...]
exb.c 78 /* mtdcr needs a constant */
80 case 0: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B0CR); break;
81 case 1: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B1CR); break;
82 case 2: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B2CR); break;
83 case 3: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B3CR); break;
84 case 4: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B4CR); break;
85 case 5: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B5CR); break;
86 case 6: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B6CR); break;
87 case 7: mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B7CR); break;
ecc_plb.c 149 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
152 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR);
157 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
158 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff);
231 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
234 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
235 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff);
269 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
  /src/sys/arch/powerpc/include/ibm4xx/
cpu.h 94 mtdcr(const int reg, uint32_t val) function in typeref:typename:__always_inline void
96 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val));
111 mtdcr(DCR_CPR0_CFGADDR, reg);
112 mtdcr(DCR_CPR0_CFGDATA, val);
118 mtdcr(DCR_CPR0_CFGADDR, reg);
125 mtdcr(DCR_SDR0_CFGADDR, reg);
126 mtdcr(DCR_SDR0_CFGDATA, val);
132 mtdcr(DCR_SDR0_CFGADDR, reg);
  /src/sys/arch/evbppc/obs405/
obs200_autoconf.c 58 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
obs266_autoconf.c 58 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
obs200_locore.S 143 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
144 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM. Just in case */
obs600_autoconf.c 103 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
obs200_machdep.c 129 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
  /src/sys/arch/powerpc/ibm4xx/
pic_uic.c 80 * cleared by mtdcr, no matter whether sync (= eieio) and/or
117 mtdcr(DCR_EXISR, v);
123 mtdcr(DCR_EXIER, v);
170 mtdcr(DCR_UIC0_BASE + DCR_UIC_SR, v);
176 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, v);
219 mtdcr(DCR_UIC1_BASE + DCR_UIC_SR, v);
225 mtdcr(DCR_UIC1_BASE + DCR_UIC_ER, v);
275 mtdcr(DCR_UIC2_BASE + DCR_UIC_SR, v);
281 mtdcr(DCR_UIC2_BASE + DCR_UIC_ER, v);
  /src/sys/arch/evbppc/dht/
autoconf.c 66 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
locore.S 133 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
134 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM.
machdep.c 147 mtdcr(DCR_SDRAM0_CFGADDR, addr);
169 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
  /src/sys/arch/evbppc/virtex/
dcr.h 78 case (addr): mtdcr((base) + (addr) / 4, val); break
idcr.h 79 #define mtidcr(addr, val) mtdcr(IDCR_BASE + (addr), (val))
virtex_start.S 121 mtdcr DCR_OCM0_DSCNTL,%r0 /* Disable Data access to OCM */
  /src/sys/arch/evbppc/walnut/
autoconf.c 69 mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
machdep.c 107 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0);
  /src/sys/arch/powerpc/ibm4xx/openbios/
locore.S 142 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
143 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM. Just in case */
  /src/sys/arch/evbppc/explora/
machdep.c 103 mtdcr(DCR_EXIER, 0);

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