| /src/external/gpl3/gdb/dist/sim/testsuite/riscv/ |
| m-ext.s | 11 mulhu x0, x1, x2
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/riscv/ |
| m-ext.s | 11 mulhu x0, x1, x2
|
| /src/external/lgpl3/gmp/dist/mpn/riscv/64/ |
| aorsmul_1.asm | 62 mulhu a7, a7, v0
|
| mul_1.asm | 48 mulhu a7, a7, v0
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| microblaze-opcm.h | 30 mulh, mulhu, mulhsu, swapb, swaph, enumerator in enum:microblaze_instr
|
| microblaze-opc.h | 150 {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
|
| rl78-decode.opc | 763 rl78->syntax = "mulhu"; ID(mulhu);
|
| rl78-decode.c | 5169 rl78->syntax = "mulhu"; ID(mulhu);
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| microblaze-opcm.h | 30 mulh, mulhu, mulhsu, swapb, swaph, enumerator in enum:microblaze_instr
|
| microblaze-opc.h | 150 {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
|
| rl78-decode.opc | 763 rl78->syntax = "mulhu"; ID(mulhu);
|
| rl78-decode.c | 5169 rl78->syntax = "mulhu"; ID(mulhu);
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| microblaze-opcm.h | 30 mulh, mulhu, mulhsu, swapb, swaph, enumerator in enum:microblaze_instr
|
| microblaze-opc.h | 150 {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
|
| rl78-decode.opc | 763 rl78->syntax = "mulhu"; ID(mulhu);
|
| rl78-decode.c | 5169 rl78->syntax = "mulhu"; ID(mulhu);
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| microblaze-opcm.h | 30 mulh, mulhu, mulhsu, swapb, swaph, enumerator in enum:microblaze_instr
|
| microblaze-opc.h | 150 {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
|
| rl78-decode.opc | 763 rl78->syntax = "mulhu"; ID(mulhu);
|
| rl78-decode.c | 5169 rl78->syntax = "mulhu"; ID(mulhu);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| KnownBits.h | 308 static KnownBits mulhu(const KnownBits &LHS, const KnownBits &RHS);
|
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| KnownBits.cpp | 504 KnownBits KnownBits::mulhu(const KnownBits &LHS, const KnownBits &RHS) { function in class:KnownBits
|
| /src/external/gpl3/gdb.old/dist/sim/riscv/ |
| sim-main.c | 644 mulhu (uint64_t a, uint64_t b)
673 uint64_t res = mulhu (a < 0 ? -a : a, b < 0 ? -b : b);
681 uint64_t res = mulhu (a < 0 ? -a : a, b);
769 TRACE_INSN (cpu, "mulhu %s, %s, %s; // %s = %s * %s",
775 store_rd (cpu, rd, mulhu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
642 mulhu (uint64_t a, uint64_t b) function
|
| /src/external/gpl3/gdb/dist/sim/riscv/ |
| sim-main.c | 644 mulhu (uint64_t a, uint64_t b)
673 uint64_t res = mulhu (a < 0 ? -a : a, b < 0 ? -b : b);
681 uint64_t res = mulhu (a < 0 ? -a : a, b);
769 TRACE_INSN (cpu, "mulhu %s, %s, %s; // %s = %s * %s",
775 store_rd (cpu, rd, mulhu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
642 mulhu (uint64_t a, uint64_t b) function
|
| /src/external/gpl3/binutils/dist/include/opcode/ |
| riscv-opc.h | 4406 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
|
