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    Searched refs:num_slices_h (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
amdgpu_dc_dsc.c 571 int num_slices_h; local in function:setup_dsc_config
709 num_slices_h = min_slices_h;
712 num_slices_h = min(policy.max_slices_h, max_slices_h);
714 num_slices_h = max_slices_h;
720 num_slices_h = min(policy.max_slices_h, max_slices_h);
722 num_slices_h = max_slices_h;
724 num_slices_h = min_slices_h;
732 dsc_cfg->num_slices_h = num_slices_h;
733 slice_width = pic_width / num_slices_h;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dsc.c 182 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
339 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
351 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
368 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
380 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
539 reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf;
565 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
dcn20_dsc.h 546 uint32_t num_slices_h; member in struct:dsc_reg_values
amdgpu_dcn20_resource.c 1928 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2311 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 438 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
439 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
449 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
amdgpu_dc_stream.c 115 stream->timing.dsc_cfg.num_slices_h = 0;
amdgpu_dc.c 2018 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 705 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ member in struct:dc_dsc_config

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