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    Searched refs:number_of_channels (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c 1235 dc->dcn_soc->number_of_channels == 1)
1449 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1450 ASSERT(dc->dcn_soc->number_of_channels < 3);
1451 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1452 dc->dcn_soc->number_of_channels = 2;
1454 if (dc->dcn_soc->number_of_channels == 1) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
dcn_calcs.h 136 float number_of_channels; member in struct:dcn_bw_internal_vars
578 int number_of_channels; member in struct:dcn_soc_bounding_box
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 116 .number_of_channels = 2,
786 v->number_of_channels = dc->dcn_soc->number_of_channels;
1132 (ddr4_dram_factor_single_Channel * v->number_of_channels));
1345 unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1466 dc->dcn_soc->number_of_channels *
1470 dc->dcn_soc->number_of_channels *
1474 dc->dcn_soc->number_of_channels *
1599 "number_of_channels: %d\n"
1633 dc->dcn_soc->number_of_channels,
    [all...]
amdgpu_dcn_calc_auto.c 257 v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i];
1298 v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw;

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