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  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
nouveau_dispnv04_disp.c 44 struct nv04_display *disp = nv04_display(dev);
82 struct nv04_display *disp = nv04_display(dev);
170 struct nv04_display *disp = nv04_display(dev);
202 struct nv04_display *disp;
disp.h 81 struct nv04_display { struct
90 static inline struct nv04_display *
91 nv04_display(struct drm_device *dev) function in typeref:struct:nv04_display *
96 /* nv04_display.c */
nouveau_dispnv04_dfp.c 100 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
127 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
142 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
211 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
241 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
242 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
255 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
292 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
293 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
468 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control
    [all...]
nouveau_dispnv04_crtc.c 67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
612 struct nv04_display *disp = nv04_display(crtc->dev);
658 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk)
    [all...]
nouveau_dispnv04_cursor.c 47 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nouveau_dispnv04_tvnv04.c 84 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
112 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
151 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
nouveau_dispnv04_dac.c 436 uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1];
461 (nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
nouveau_dispnv04_hw.c 309 nv04_display(dev)->saved_vga_font[plane][i] =
312 nv04_display(dev)->saved_vga_font[plane][i] =
318 nv04_display(dev)->saved_vga_font[plane][i]);
320 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],
hw.h 378 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
nouveau_dispnv04_tvnv17.c 408 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
469 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
nouveau_dispnv04_tvmodesnv17.c 552 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];

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