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      1 /*	$NetBSD: nouveau_nvkm_engine_fifo_nv40.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_nv40.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
     28 
     29 #include "nv04.h"
     30 #include "channv04.h"
     31 #include "regsnv04.h"
     32 
     33 #include <core/ramht.h>
     34 #include <subdev/fb.h>
     35 #include <subdev/instmem.h>
     36 
     37 static const struct nv04_fifo_ramfc
     38 nv40_fifo_ramfc[] = {
     39 	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
     40 	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
     41 	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
     42 	{ 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
     43 	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
     44 	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
     45 	{ 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
     46 	{  2, 28, 0x18, 28, 0x002058 },
     47 	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
     48 	{ 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
     49 	{ 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
     50 	{ 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
     51 	{ 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
     52 	{ 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
     53 	{ 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
     54 	{ 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
     55 	{ 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
     56 	{ 32,  0, 0x40,  0, 0x0032e4 },
     57 	{ 32,  0, 0x44,  0, 0x0032e8 },
     58 	{ 32,  0, 0x4c,  0, 0x002088 },
     59 	{ 32,  0, 0x50,  0, 0x003300 },
     60 	{ 32,  0, 0x54,  0, 0x00330c },
     61 	{}
     62 };
     63 
     64 static void
     65 nv40_fifo_init(struct nvkm_fifo *base)
     66 {
     67 	struct nv04_fifo *fifo = nv04_fifo(base);
     68 	struct nvkm_device *device = fifo->base.engine.subdev.device;
     69 	struct nvkm_fb *fb = device->fb;
     70 	struct nvkm_instmem *imem = device->imem;
     71 	struct nvkm_ramht *ramht = imem->ramht;
     72 	struct nvkm_memory *ramro = imem->ramro;
     73 	struct nvkm_memory *ramfc = imem->ramfc;
     74 
     75 	nvkm_wr32(device, 0x002040, 0x000000ff);
     76 	nvkm_wr32(device, 0x002044, 0x2101ffff);
     77 	nvkm_wr32(device, 0x002058, 0x00000001);
     78 
     79 	nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
     80 					    ((ramht->bits - 9) << 16) |
     81 					    (ramht->gpuobj->addr >> 8));
     82 	nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
     83 
     84 	switch (device->chipset) {
     85 	case 0x47:
     86 	case 0x49:
     87 	case 0x4b:
     88 		nvkm_wr32(device, 0x002230, 0x00000001);
     89 		/* fall through */
     90 	case 0x40:
     91 	case 0x41:
     92 	case 0x42:
     93 	case 0x43:
     94 	case 0x45:
     95 	case 0x48:
     96 		nvkm_wr32(device, 0x002220, 0x00030002);
     97 		break;
     98 	default:
     99 		nvkm_wr32(device, 0x002230, 0x00000000);
    100 		nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +
    101 					      nvkm_memory_addr(ramfc)) >> 16) |
    102 					    0x00030000);
    103 		break;
    104 	}
    105 
    106 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1);
    107 
    108 	nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
    109 	nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
    110 
    111 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
    112 	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
    113 	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
    114 }
    115 
    116 static const struct nvkm_fifo_func
    117 nv40_fifo = {
    118 	.init = nv40_fifo_init,
    119 	.intr = nv04_fifo_intr,
    120 	.pause = nv04_fifo_pause,
    121 	.start = nv04_fifo_start,
    122 	.chan = {
    123 		&nv40_fifo_dma_oclass,
    124 		NULL
    125 	},
    126 };
    127 
    128 int
    129 nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
    130 {
    131 	return nv04_fifo_new_(&nv40_fifo, device, index, 32,
    132 			      nv40_fifo_ramfc, pfifo);
    133 }
    134