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    Searched refs:nv_funcs (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_pp_smu.c 1004 funcs->nv_funcs.pp_smu.dm = ctx;
1005 funcs->nv_funcs.set_display_count = pp_nv_set_display_count;
1006 funcs->nv_funcs.set_hard_min_dcfclk_by_freq =
1008 funcs->nv_funcs.set_min_deep_sleep_dcfclk =
1010 funcs->nv_funcs.set_voltage_by_freq =
1012 funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;
1015 funcs->nv_funcs.set_pme_wa_enable = NULL;
1017 funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
1019 funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
1021 funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_pp_smu.h 288 struct pp_smu_funcs_nv nv_funcs; member in union:pp_smu_funcs::__anond71392a4010a
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 181 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
348 pp_smu = &clk_mgr->pp_smu->nv_funcs;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 3453 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3454 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3455 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3460 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3461 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3462 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3664 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3665 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);

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