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Searched
refs:nvif_rd32
(Results
1 - 16
of
16
) sorted by relevancy
/src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_backlight.c
76
int val = (
nvif_rd32
(device, NV40_PMC_BACKLIGHT) &
89
int reg =
nvif_rd32
(device, NV40_PMC_BACKLIGHT);
111
if (!(
nvif_rd32
(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))
130
val =
nvif_rd32
(device, NV50_PDISP_SOR_PWM_CTL(or));
165
div =
nvif_rd32
(device, NV50_PDISP_SOR_PWM_DIV(or));
166
val =
nvif_rd32
(device, NV50_PDISP_SOR_PWM_CTL(or));
183
div =
nvif_rd32
(device, NV50_PDISP_SOR_PWM_DIV(or));
210
if (!
nvif_rd32
(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1)))
nouveau_led.c
49
div =
nvif_rd32
(device, 0x61c880) & 0x00ffffff;
50
duty =
nvif_rd32
(device, 0x61c884) & 0x00ffffff;
nouveau_nv10_fence.c
58
return
nvif_rd32
(&chan->user, 0x0048);
nouveau_dma.c
73
val =
nvif_rd32
(&chan->user, chan->user_get);
75
val |= (uint64_t)
nvif_rd32
(&chan->user, chan->user_get_hi) << 32;
129
uint32_t get =
nvif_rd32
(&chan->user, 0x88);
nouveau_svm.c
448
const u32 instlo =
nvif_rd32
(memory, offset + 0x00);
449
const u32 insthi =
nvif_rd32
(memory, offset + 0x04);
450
const u32 addrlo =
nvif_rd32
(memory, offset + 0x08);
451
const u32 addrhi =
nvif_rd32
(memory, offset + 0x0c);
452
const u32 timelo =
nvif_rd32
(memory, offset + 0x10);
453
const u32 timehi =
nvif_rd32
(memory, offset + 0x14);
454
const u32 engine =
nvif_rd32
(memory, offset + 0x18);
455
const u32 info =
nvif_rd32
(memory, offset + 0x1c);
605
buffer->put =
nvif_rd32
(device, buffer->putaddr);
606
buffer->get =
nvif_rd32
(device, buffer->getaddr)
[
all
...]
nouveau_debugfs.c
66
nvif_rd32
(&drm->client.device.object, 0x101000));
nouveau_bios.c
244
sel_clk_binding =
nvif_rd32
(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
340
return
nvif_rd32
(device, 0x001800) & 0x0000000f;
343
return (
nvif_rd32
(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
345
return (
nvif_rd32
(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
675
sel_clk_binding =
nvif_rd32
(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
1957
nvif_wr32(device, NV_PBUS_DEBUG_4,
nvif_rd32
(device, NV_PBUS_DEBUG_4) | 0x18);
/src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
nouveau_dispnv04_arb.c
207
uint32_t cfg1 =
nvif_rd32
(device, NV04_PFB_CFG1);
227
sim_data.memory_type =
nvif_rd32
(device, NV04_PFB_CFG0) & 0x1;
228
sim_data.memory_width = (
nvif_rd32
(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
nouveau_dispnv04_dac.c
88
if (!(
nvif_rd32
(device, NV_PRMCIO_INP0__COLOR) & 1))
94
if ( (
nvif_rd32
(device, NV_PRMCIO_INP0__COLOR) & 1))
100
if (!(
nvif_rd32
(device, NV_PRMCIO_INP0__COLOR) & 1))
268
saved_powerctrl_2 =
nvif_rd32
(device, NV_PBUS_POWERCTRL_2);
272
saved_powerctrl_4 =
nvif_rd32
(device, NV_PBUS_POWERCTRL_4);
hw.h
68
val =
nvif_rd32
(device, reg);
88
val =
nvif_rd32
(device, reg);
267
return !!(
nvif_rd32
(device, NV_PBUS_DEBUG_1) & (1 << 28));
tvnv17.h
142
return
nvif_rd32
(&device->object, reg);
nouveau_dispnv04_hw.c
182
pll1 =
nvif_rd32
(device, reg1);
184
pll2 =
nvif_rd32
(device, reg1 + 4);
188
pll2 =
nvif_rd32
(device, reg2);
793
if ( (
nvif_rd32
(device, NV_PRMCIO_INP0__COLOR) & 8))
797
if (!(
nvif_rd32
(device, NV_PRMCIO_INP0__COLOR) & 8))
nouveau_dispnv04_overlay.c
436
nvif_wr32(dev, NV_PVIDEO_SU_STATE,
nvif_rd32
(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16));
nouveau_dispnv04_dfp.c
344
if (
nvif_rd32
(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
/src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/
object.h
81
nvif_rd32
(struct nvif_object *obj, uint64_t offset)
function in typeref:typename:uint32_t
134
#define
nvif_rd32
(a,b) ({ ((u32)nvif_rd((a), ioread32_native, 4, (b))); })
macro
141
u32 _addr = (b), _data =
nvif_rd32
(__object, _addr); \
/src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/
nouveau_dispnv50_disp.c
228
if (!(
nvif_rd32
(&device->object, 0x070000) & 0x00000002))
239
u32 put =
nvif_rd32
(&dmac->base.user, 0x0000) / 4;
248
if (!
nvif_rd32
(&dmac->base.user, 0x0004))
2513
crtcs =
nvif_rd32
(&device->object, 0x610060) & 0xff;
2516
crtcs =
nvif_rd32
(&device->object, 0x612004) & 0xf;
Completed in 24 milliseconds
Indexes created Thu Oct 16 14:10:15 GMT 2025