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    Searched refs:nvkm_debug (Results 1 - 25 of 76) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/nvfw/
nouveau_nvkm_nvfw_fw.c 34 nvkm_debug(subdev, "binHdr:\n");
35 nvkm_debug(subdev, "\tbinMagic : 0x%08x\n", hdr->bin_magic);
36 nvkm_debug(subdev, "\tbinVer : %d\n", hdr->bin_ver);
37 nvkm_debug(subdev, "\tbinSize : %d\n", hdr->bin_size);
38 nvkm_debug(subdev, "\theaderOffset : 0x%x\n", hdr->header_offset);
39 nvkm_debug(subdev, "\tdataOffset : 0x%x\n", hdr->data_offset);
40 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
48 nvkm_debug(subdev, "blDesc\n");
49 nvkm_debug(subdev, "\tstartTag : 0x%x\n", hdr->start_tag);
50 nvkm_debug(subdev, "\tdmemLoadOff : 0x%x\n", hdr->dmem_load_off)
    [all...]
nouveau_nvkm_nvfw_flcn.c 33 nvkm_debug(subdev, "loaderConfig\n");
34 nvkm_debug(subdev, "\tdmaIdx : %d\n", hdr->dma_idx);
35 nvkm_debug(subdev, "\tcodeDmaBase : 0x%xx\n", hdr->code_dma_base);
36 nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
37 nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
38 nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
39 nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base);
40 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
41 nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base);
42 nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc)
    [all...]
nouveau_nvkm_nvfw_hs.c 34 nvkm_debug(subdev, "hsHeader:\n");
35 nvkm_debug(subdev, "\tsigDbgOffset : 0x%x\n", hdr->sig_dbg_offset);
36 nvkm_debug(subdev, "\tsigDbgSize : 0x%x\n", hdr->sig_dbg_size);
37 nvkm_debug(subdev, "\tsigProdOffset : 0x%x\n", hdr->sig_prod_offset);
38 nvkm_debug(subdev, "\tsigProdSize : 0x%x\n", hdr->sig_prod_size);
39 nvkm_debug(subdev, "\tpatchLoc : 0x%x\n", hdr->patch_loc);
40 nvkm_debug(subdev, "\tpatchSig : 0x%x\n", hdr->patch_sig);
41 nvkm_debug(subdev, "\thdrOffset : 0x%x\n", hdr->hdr_offset);
42 nvkm_debug(subdev, "\thdrSize : 0x%x\n", hdr->hdr_size);
52 nvkm_debug(subdev, "hsLoadHeader:\n")
    [all...]
nouveau_nvkm_nvfw_acr.c 33 nvkm_debug(subdev, "wprHeader\n");
34 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);
35 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);
36 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
37 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
38 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status);
44 nvkm_debug(subdev, "wprHeader\n");
45 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);
46 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);
47 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner)
    [all...]
nouveau_nvkm_nvfw_ls.c 36 nvkm_debug(subdev, "lsUcodeImgDesc:\n");
37 nvkm_debug(subdev, "\tdescriptorSize : %d\n",
39 nvkm_debug(subdev, "\timageSize : %d\n", hdr->image_size);
40 nvkm_debug(subdev, "\ttoolsVersion : 0x%x\n",
42 nvkm_debug(subdev, "\tappVersion : 0x%x\n", hdr->app_version);
45 nvkm_debug(subdev, "\tdate : %s\n", date);
48 nvkm_debug(subdev, "\tbootloaderStartOffset: 0x%x\n",
50 nvkm_debug(subdev, "\tbootloaderSize : 0x%x\n",
52 nvkm_debug(subdev, "\tbootloaderImemOffset : 0x%x\n",
54 nvkm_debug(subdev, "\tbootloaderEntryPoint : 0x%x\n"
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/timer/
nouveau_nvkm_subdev_timer_nv41.c 65 nvkm_debug(subdev, "input frequency : %dHz\n", f);
66 nvkm_debug(subdev, "input multiplier: %d\n", m);
67 nvkm_debug(subdev, "numerator : %08x\n", n);
68 nvkm_debug(subdev, "denominator : %08x\n", d);
69 nvkm_debug(subdev, "timer frequency : %dHz\n", (f * m) * d / n);
nouveau_nvkm_subdev_timer_nv40.c 70 nvkm_debug(subdev, "input frequency : %dHz\n", f);
71 nvkm_debug(subdev, "numerator : %08x\n", n);
72 nvkm_debug(subdev, "denominator : %08x\n", d);
73 nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
nouveau_nvkm_subdev_timer_nv04.c 40 nvkm_debug(subdev, "time low : %08x\n", lo);
41 nvkm_debug(subdev, "time high : %08x\n", hi);
133 nvkm_debug(subdev, "input frequency : %dHz\n", f);
134 nvkm_debug(subdev, "numerator : %08x\n", n);
135 nvkm_debug(subdev, "denominator : %08x\n", d);
136 nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mxm/
nouveau_nvkm_subdev_mxm_base.c 127 nvkm_debug(subdev, "DSM MXMS failed\n");
135 nvkm_debug(subdev, "DSM MXMS returned 0x%"PRIx64"\n",
160 nvkm_debug(subdev, "WMMX MXMI returned %d\n", status);
167 nvkm_debug(subdev, "WMMX MXMI version %d.%d\n",
171 nvkm_debug(subdev, "WMMX MXMI returned non-integer\n");
189 nvkm_debug(subdev, "WMMX GUID not found\n");
201 nvkm_debug(subdev, "WMMX MXMS returned %d\n", status);
235 nvkm_debug(&mxm->subdev, "checking %s\n", shadow->name);
265 nvkm_debug(&mxm->subdev, "no VBIOS data, nothing to do\n");
270 nvkm_debug(&mxm->subdev, "module flags: %02x\n"
    [all...]
nouveau_nvkm_subdev_mxm_mxms.c 55 nvkm_debug(&mxm->subdev, "unknown version %d.%d\n", mxms[4], mxms[5]);
79 nvkm_debug(&mxm->subdev, "checksum invalid\n");
90 nvkm_debug(&mxm->subdev, "signature invalid\n");
149 nvkm_debug(subdev, "unknown descriptor type %d\n", type);
167 nvkm_debug(subdev, "%4s: %s\n", mxms_desc[type], data);
172 nvkm_debug(subdev, " %s\n", data);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bus/
nouveau_nvkm_subdev_bus_hwsq.c 98 nvkm_debug(hwsq->subdev, "R[%06x] = %08x\n", addr, data);
123 nvkm_debug(hwsq->subdev, " FLAG[%02x] = %d\n", flag, data);
135 nvkm_debug(hwsq->subdev, " WAIT[%02x] = %d\n", flag, data);
162 nvkm_debug(subdev, "WAIT VBLANK !NO ACTIVE HEAD\n");
166 nvkm_debug(subdev, "WAIT VBLANK HEAD%d\n", head_sync);
180 nvkm_debug(hwsq->subdev, " DELAY = %d ns\n", nsec);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/
nouveau_nvkm_subdev_pmu_memx.c 96 nvkm_debug(subdev, "Exec took %uns, PMU_IN %08x\n",
107 nvkm_debug(&memx->pmu->subdev, "R[%06x] = %08x\n", addr, data);
115 nvkm_debug(&memx->pmu->subdev, "R[%06x] & %08x == %08x, %d us\n",
124 nvkm_debug(&memx->pmu->subdev, " DELAY = %d ns\n", nsec);
154 nvkm_debug(subdev, "WAIT VBLANK !NO ACTIVE HEAD\n");
158 nvkm_debug(subdev, "WAIT VBLANK HEAD%d\n", head_sync);
166 nvkm_debug(&memx->pmu->subdev, " MEM TRAIN\n");
199 nvkm_debug(&memx->pmu->subdev, " HOST BLOCKED\n");
206 nvkm_debug(&memx->pmu->subdev, " HOST UNBLOCKED\n");
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bios/
nouveau_nvkm_subdev_bios_shadow.c 70 nvkm_debug(subdev, "%08x: header fetch failed\n",
76 nvkm_debug(subdev, "image %d invalid\n", idx);
80 nvkm_debug(subdev, "%08x: type %02x, %d bytes\n",
84 nvkm_debug(subdev, "%08x: fetch failed\n", image.base);
92 nvkm_debug(subdev, "%08x: checksum failed\n",
120 nvkm_debug(subdev, "trying %s...\n", name ? name : func->name);
131 nvkm_debug(subdev, "scored %d\n", mthd->score);
241 nvkm_debug(subdev, "using image from %s\n", best->func ?
nouveau_nvkm_subdev_bios_shadowramin.c 78 nvkm_debug(subdev, "... display disabled\n");
91 nvkm_debug(subdev, "... not enabled\n");
95 nvkm_debug(subdev, "... not in vram\n");
nouveau_nvkm_subdev_bios_image.c 50 nvkm_debug(subdev, "%08x: ROM signature (%04x) unknown\n",
nouveau_nvkm_subdev_bios_npde.c 44 nvkm_debug(&bios->subdev,
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pci/
nouveau_nvkm_subdev_pci_pcie.c 88 nvkm_debug(&pci->subdev, "pcie max speed: %s\n",
148 nvkm_debug(subdev, "%s not supported by bus or card, dropping"
158 nvkm_debug(subdev, "requested matches current speed\n");
162 nvkm_debug(subdev, "set link to %s x%i\n",
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/volt/
nouveau_nvkm_subdev_volt_gk20a.c 118 nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv);
131 nvkm_debug(subdev, "prev=%d, target=%d, condition=%d\n",
162 nvkm_debug(&volt->base.subdev, "the default voltage is %duV\n", uv);
172 nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i,
nouveau_nvkm_subdev_volt_base.c 81 nvkm_debug(subdev, "set req %duv to %duv: %d\n", uv,
202 nvkm_debug(subdev, "found ranged based VIDs\n");
216 nvkm_debug(subdev, "found entry based VIDs\n");
252 nvkm_debug(subdev, "current voltage unknown\n");
255 nvkm_debug(subdev, "current voltage: %duv\n", ret);
266 nvkm_debug(&volt->subdev, "speedo %x\n", volt->speedo);
303 nvkm_debug(&volt->subdev, "min: %iuv max: %iuv\n",
319 nvkm_debug(&volt->subdev, "VID %02x: %duv\n",
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
nouveau_nvkm_subdev_clk_mcp77.c 165 nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
278 nvkm_debug(subdev, "nvpll: %08x %08x %08x\n",
280 nvkm_debug(subdev, " spll: %08x %08x %08x\n",
282 nvkm_debug(subdev, " vdiv: %08x\n", clk->vdiv);
284 nvkm_debug(subdev, "core: hrefm4\n");
286 nvkm_debug(subdev, "core: nvpll\n");
289 nvkm_debug(subdev, "shader: hrefm4\n");
291 nvkm_debug(subdev, "shader: nvpll\n");
293 nvkm_debug(subdev, "shader: spll\n");
296 nvkm_debug(subdev, "vdec: 500MHz\n")
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/core/
nouveau_nvkm_core_firmware.c 97 nvkm_debug(subdev, "firmware \"%s\" loaded - %zu byte(s)\n",
102 nvkm_debug(subdev, "firmware \"%s\" unavailable\n", f);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/therm/
nouveau_nvkm_subdev_therm_fan.c 54 nvkm_debug(subdev, "FAN target: %d\n", target);
81 nvkm_debug(subdev, "FAN update: %d\n", duty);
254 nvkm_debug(subdev, "GPIO_FAN is in input mode\n");
270 nvkm_debug(subdev, "FAN control: %s\n", therm->fan->type);
290 nvkm_debug(subdev, "parsing the fan table failed\n");
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/ibus/
nouveau_nvkm_subdev_ibus_gf100.c 38 nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
49 nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
60 nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
nouveau_nvkm_subdev_ibus_gk104.c 38 nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
49 nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
60 nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
nouveau_nvkm_subdev_ibus_gk20a.c 60 nvkm_debug(ibus, "resetting ibus ring\n");

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