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    Searched refs:ocsc_mode (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mpc.c 141 enum mpc_output_csc_mode ocsc_mode)
147 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) {
148 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
166 ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
168 ocsc_mode = MPC_OUTPUT_CSC_COEF_B;
175 if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) {
188 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
195 enum mpc_output_csc_mode ocsc_mode)
203 if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) {
204 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
    [all...]
dcn20_mpc.h 297 enum mpc_output_csc_mode ocsc_mode);
303 enum mpc_output_csc_mode ocsc_mode);
amdgpu_dcn20_hwseq.c 719 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; local
730 ocsc_mode);
736 ocsc_mode);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
mpc.h 239 enum mpc_output_csc_mode ocsc_mode);
244 enum mpc_output_csc_mode ocsc_mode);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_dpp_cm.c 193 uint32_t ocsc_mode; local
213 ocsc_mode = 4;
215 ocsc_mode = 5;
223 if (ocsc_mode == 4) {
240 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);

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