| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| dce120_timing_generator.h | 40 const struct dce110_timing_generator_offsets *offsets);
|
| amdgpu_dce120_timing_generator.c | 48 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
51 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
98 tg110->offsets.crtc);
181 tg110->offsets.crtc);
197 tg110->offsets.crtc);
208 tg110->offsets.crtc);
258 tg110->offsets.crtc);
266 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);
320 tg110->offsets.crtc);
382 tg110->offsets.crtc)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| dce80_timing_generator.h | 39 const struct dce110_timing_generator_offsets *offsets);
|
| amdgpu_dce80_timing_generator.c | 88 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
89 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
90 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
96 + DCE110TG_FROM_TG(tg)->offsets.dmif;
233 const struct dce110_timing_generator_offsets *offsets)
237 tg110->offsets = *offsets;
|
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/device_include/ |
| svga_overlay.h | 127 * Computes the size, pitches and offsets for YUV frames.
133 * Pitches and offsets for the given YUV frame are put in 'pitches'
134 * and 'offsets' respectively. They are both optional though.
145 uint32 *offsets) /* OUT (optional) */
151 if (offsets) {
152 offsets[0] = 0;
164 if (offsets) {
165 offsets[1] = *size;
177 if (offsets) {
178 offsets[2] = *size
[all...] |
| /src/lib/libc/gen/ |
| errlist.awk | 58 offsets[number] = offset;
103 offsets[errno++] = offset;
105 printf("\t%d,\n", offsets[j]);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_object.c | 76 memset(obj->mmo.offsets, 0, sizeof(obj->mmo.offsets));
78 obj->mmo.offsets = RB_ROOT;
137 if ((mmo = obj->mmo.offsets[t]) == NULL)
143 rbtree_postorder_for_each_entry_safe(mmo, mn, &obj->mmo.offsets, offset)
233 if ((mmo = obj->mmo.offsets[t]) == NULL)
240 memset(obj->mmo.offsets, 0, sizeof(obj->mmo.offsets));
243 &obj->mmo.offsets,
249 obj->mmo.offsets = RB_ROOT
[all...] |
| i915_gem_object_types.h | 144 spinlock_t lock; /* Protects access to mmo offsets */
146 struct i915_mmap_offset *offsets[I915_MMAP_NTYPES]; member in struct:drm_i915_gem_object::__anonbfddbbad0308
148 struct rb_root offsets; member in struct:drm_i915_gem_object::__anonbfddbbad0308
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| dce110_compressor.h | 42 struct dce110_compressor_reg_offsets offsets; member in struct:dce110_compressor
|
| dce110_timing_generator.h | 100 struct dce110_timing_generator_offsets offsets; member in struct:dce110_timing_generator
126 const struct dce110_timing_generator_offsets *offsets);
|
| amdgpu_dce110_compressor.c | 48 (reg + cp110->offsets.dcp_offset)
50 (reg + cp110->offsets.dmif_offset)
86 cp110->offsets = reg_offsets[crtc_inst];
312 cp110->offsets = reg_offsets[params->inst];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| dce112_compressor.h | 42 struct dce112_compressor_reg_offsets offsets; member in struct:dce112_compressor
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| i915_gem_coherency.c | 312 u32 *offsets, *values; local in function:igt_gem_coherency
324 offsets = kmalloc_array(ncachelines, 2*sizeof(u32), GFP_KERNEL);
325 if (!offsets)
328 offsets[count] = count * 64 + 4 * (count % 16);
330 values = offsets + ncachelines;
368 i915_random_reorder(offsets, ncachelines, &prng);
373 err = over->set(&ctx, offsets[n], ~values[n]);
382 err = write->set(&ctx, offsets[n], values[n]);
393 err = read->get(&ctx, offsets[n], &found);
405 ~values[n], offsets[n])
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_client_modeset.c | 266 struct drm_client_offset *offsets,
345 struct drm_client_offset *offsets,
369 offsets[idx].x = hoffset;
370 offsets[idx].y = voffset;
378 struct drm_client_offset *offsets,
422 * find the tile offsets for this pass - need to find
425 drm_client_get_tile_offsets(connectors, connector_count, modes, offsets, i,
570 struct drm_client_offset *offsets,
774 struct drm_client_offset *offsets; local in function:drm_client_modeset_probe
809 offsets = kcalloc(connector_count, sizeof(*offsets), GFP_KERNEL)
[all...] |
| drm_modeset_helper.c | 96 fb->offsets[i] = mode_cmd->offsets[i];
|
| /src/sys/arch/pmax/stand/smallnet/setnetimage/ |
| setnetimage.c | 71 #define NLADDR(x) (mappedbfile + offsets[(x)])
80 size_t offsets[X_NSYMS]; local in function:main
122 if (findoff_elf32(mappedbfile, osb.st_size, nl[i].n_value, &offsets[i]) != 0)
125 printf("%s is at offset %#x in %s\n", nl[i].n_name, offsets[i], bootfile);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| mkregtable.c | 117 struct list_head offsets; member in struct:table
138 list_add_tail(&offset->list, &t->offsets);
143 INIT_LIST_HEAD(&t->offsets);
184 list_for_each_entry(offset, &t->offsets, list) {
|
| /src/sys/arch/hpcmips/dev/ |
| mq200subr.c | 195 static int offsets[MQ200_I_MAX] = { local in function:mq200_setup_regctx
205 for (i = 0; i < sizeof(offsets)/sizeof(*offsets); i++) {
206 if (offsets[i] == 0)
212 sc->sc_regctxs[i].offset = offsets[i];
|
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_binding.c | 138 * @offsets: array[shader_slot] of offsets to the array[slot]
147 const size_t *offsets; member in struct:vmw_binding_info
192 .offsets = vmw_binding_shader_offsets,
196 .offsets = vmw_binding_rt_offsets,
200 .offsets = vmw_binding_tex_offsets,
204 .offsets = vmw_binding_cb_offsets,
208 .offsets = vmw_binding_shader_offsets,
212 .offsets = vmw_binding_rt_offsets,
216 .offsets = vmw_binding_sr_offsets
[all...] |
| /src/sys/arch/amiga/stand/loadkmap/din/ |
| din-kbdmap.c | 423 /* string table. If there's a better way to get the offsets into the
|
| /src/sys/arch/amiga/stand/loadkmap/pl_din/ |
| pl_din-kbdmap.c | 428 /* string table. If there's a better way to get the offsets into the
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_framebuffer.h | 154 * @offsets: Offset from buffer start to the actual pixel data in bytes,
163 * @offsets must at least be tile-size aligned, but hardware often has
166 * This should not be used to specifiy x/y pixel offsets into the buffer
170 unsigned int offsets[4]; member in struct:drm_framebuffer
|
| /src/games/rogue/ |
| level.c | 540 static short offsets[4] = {-1, 1, 3, -3}; local in function:fill_it
546 t = offsets[srow];
547 offsets[srow] = offsets[scol];
548 offsets[scol] = t;
552 target_room = rn + offsets[i];
588 recursive_deadend(rn, offsets, srow, scol);
595 recursive_deadend(short rn, const short *offsets, short srow, short scol)
604 de = rn + offsets[i];
623 recursive_deadend(de, offsets, drow, dcol)
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra_drm_fb.c | 136 fb->offsets[0] = 0;
|
| /src/sys/external/bsd/drm2/drm/ |
| drm_gem_framebuffer_helper.c | 140 + mode_cmd->offsets[plane];
|
