| /src/external/gpl3/gdb/dist/sim/mips/ |
| sim-main.c | 40 starting at physical location pAddr. The data is returned in the
59 address_word pAddr,
67 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
75 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
81 pr_addr (pAddr));
84 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
94 unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
100 value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
103 value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
106 value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
269 address_word paddr = vaddr; local
293 address_word paddr = vaddr; local
[all...] |
| sim-main.h | 984 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
985 #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
986 load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
988 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
989 #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
990 store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
992 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
993 #define CacheOp(op,pAddr,vAddr,instruction) \
994 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
| /src/external/gpl3/gdb.old/dist/sim/mips/ |
| sim-main.c | 40 starting at physical location pAddr. The data is returned in the
59 address_word pAddr,
67 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
75 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
81 pr_addr (pAddr));
84 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
94 unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
100 value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
103 value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
106 value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
269 address_word paddr = vaddr; local
293 address_word paddr = vaddr; local
[all...] |
| sim-main.h | 984 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
985 #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
986 load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
988 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
989 #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
990 store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
992 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
993 #define CacheOp(op,pAddr,vAddr,instruction) \
994 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
| /src/external/public-domain/sqlite/dist/ |
| sqlite3.c | [all...] |
