| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_mux.c | 53 if (mux->parents[index] != NULL &&
54 strcmp(mux->parents[index], name) == 0)
81 return mux->parents[index];
|
| sunxi_ccu_prediv.c | 110 if (prediv->parents[index] != NULL &&
111 strcmp(prediv->parents[index], name) == 0)
138 return prediv->parents[index];
|
| sunxi_ccu_div.c | 114 pname = div->parents[index];
197 if (div->parents[index] != NULL &&
198 strcmp(div->parents[index], name) == 0)
223 return div->parents[0];
228 return div->parents[index];
|
| sunxi_ccu.h | 158 const char **parents; member in struct:sunxi_ccu_nm
188 .u.nm.parents = (_parents), \
204 const char **parents; member in struct:sunxi_ccu_div
239 .u.div.parents = (_parents), \
266 const char **parents; member in struct:sunxi_ccu_prediv
299 .u.prediv.parents = (_parents), \
419 const char **parents; member in struct:sunxi_ccu_mux
437 .u.mux.parents = (_parents), \
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru_arm.c | 85 main_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_main]);
86 alt_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_alt]);
88 device_printf(sc->sc_dev, "couldn't get clock parents\n");
92 error = rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_alt]);
113 rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main]);
140 main_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_main]);
141 alt_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_alt]);
143 device_printf(sc->sc_dev, "couldn't get clock parents\n");
149 error = rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_alt]);
179 rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main])
[all...] |
| rk_cru_mux.c | 60 return mux->parents[index];
76 if (strcmp(mux->parents[index], parent) == 0) {
|
| rk_cru_composite.c | 171 rclk_parent = rk_cru_clock_find(sc, composite->parents[mux]);
175 clk_parent = fdtbus_clock_byname(composite->parents[mux]);
233 return composite->parents[mux];
248 if (strcmp(composite->parents[mux], parent) == 0) {
|
| rk_cru.h | 100 const char **parents; member in struct:rk_cru_pll
117 .u.pll.parents = (_parents), \
177 const char **parents; member in struct:rk_cru_arm
196 .u.arm.parents = (_parents), \
218 .u.arm.parents = (_parents), \
283 const char **parents; member in struct:rk_cru_composite
305 .u.composite.parents = (_parents), \
382 const char **parents; member in struct:rk_cru_mux
397 .u.mux.parents = (_parents), \
|
| /src/sys/arch/arm/nxp/ |
| imx_ccm_mux.c | 55 return mux->parents[sel];
68 if (strcmp(mux->parents[sel], parent) == 0) {
|
| imx_ccm_composite.c | 120 rclk_parent = imx_ccm_clock_find(sc, composite->parents[mux]);
124 clk_parent = fdtbus_clock_byname(composite->parents[mux]);
178 return composite->parents[mux];
191 if (strcmp(composite->parents[mux], parent) == 0) {
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk_mux.c | 56 return mux->parents[sel];
|
| /src/sys/arch/arm/nvidia/ |
| tegra_clock.h | 57 const char **parents; member in struct:tegra_mux_clk
|
| /src/sys/arch/arm/samsung/ |
| exynos_clock.h | 52 const char **parents; member in struct:exynos_mux_clk
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| omap443x.dtsi | 87 assigned-clock-parents = <&dpll_per_m7x2_ck>;
|
| imx6ull-colibri-wifi.dtsi | 42 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
|
| imx7ulp.dtsi | 155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
262 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
286 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
334 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
346 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
358 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
370 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
| imx7d-remarkable2.dts | 50 assigned-clock-parents = <&clks IMX7D_CKIL>;
62 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
70 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
|
| am3517.dtsi | 185 assigned-clock-parents = <&sys_ck>;
195 assigned-clock-parents = <&sys_ck>;
|
| exynos5422-odroidxu3-audio.dtsi | 66 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
|
| exynos5422-odroidxu4.dts | 61 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
|
| imx7d-meerkat96.dts | 144 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
152 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
161 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
169 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
| imx7ulp-com.dts | 41 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
|
| omap2420-n810.dts | 65 assigned-clock-parents = <&func_96m_ck>;
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/ |
| jh7110-pine64-star64.dts | 20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
28 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| k3-j721e-common-proc-board.dts | 514 assigned-clock-parents = <&k3_clks 157 400>;
571 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
645 assigned-clock-parents = <&cmn_refclk1>;
650 assigned-clock-parents = <&cmn_refclk1>;
655 assigned-clock-parents = <&cmn_refclk1>;
660 assigned-clock-parents = <&cmn_refclk1>;
665 assigned-clock-parents = <&cmn_refclk1>;
670 assigned-clock-parents = <&cmn_refclk1>;
675 assigned-clock-parents = <&wiz0_pll1_refclk>;
688 assigned-clock-parents = <&wiz1_pll1_refclk>
[all...] |
