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    Searched refs:patched_crtc_timing (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_optc.c 154 struct dc_crtc_timing patched_crtc_timing; local in function:optc1_program_timing
171 patched_crtc_timing = *dc_crtc_timing;
172 apply_front_porch_workaround(&patched_crtc_timing);
178 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
183 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
186 asic_blank_start = patched_crtc_timing.h_total -
187 patched_crtc_timing.h_front_porch;
191 patched_crtc_timing.h_border_right -
192 patched_crtc_timing.h_addressable -
193 patched_crtc_timing.h_border_left
303 struct dc_crtc_timing patched_crtc_timing; local in function:optc1_set_vtg_params
    [all...]
amdgpu_dcn10_hw_sequencer.c 3109 struct dc_crtc_timing patched_crtc_timing; local in function:dcn10_get_vupdate_offset_from_vsync
3115 patched_crtc_timing = *dc_crtc_timing;
3116 apply_front_porch_workaround(&patched_crtc_timing);
3118 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
3120 vesa_sync_start = patched_crtc_timing.v_addressable +
3121 patched_crtc_timing.v_border_bottom +
3122 patched_crtc_timing.v_front_porch;
3124 asic_blank_end = (patched_crtc_timing.v_total -
3126 patched_crtc_timing.v_border_top)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 292 struct dc_crtc_timing patched_crtc_timing; local in function:dce110_timing_generator_program_timing_generator
309 patched_crtc_timing = *dc_crtc_timing;
311 dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing);
315 bp_params.h_total = patched_crtc_timing.h_total;
317 patched_crtc_timing.h_addressable;
318 bp_params.v_total = patched_crtc_timing.v_total;
319 bp_params.v_addressable = patched_crtc_timing.v_addressable;
322 bp_params.h_sync_width = patched_crtc_timing.h_sync_width;
324 bp_params.v_sync_width = patched_crtc_timing.v_sync_width;
328 patched_crtc_timing.h_border_left
    [all...]

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