| /src/sys/dev/mii/ |
| qsphy.c | 201 uint16_t bmsr, bmcr, pctl; local
229 PHY_READ(sc, MII_QSPHY_PCTL, &pctl);
230 PHY_READ(sc, MII_QSPHY_PCTL, &pctl);
231 switch (pctl & PCTL_OPMASK) {
|
| /src/sbin/scsictl/ |
| scsi_subr.c | 99 scsi_mode_sense(int fd, u_int8_t pgcode, u_int8_t pctl, void *buf, size_t len)
107 cmd.page = pgcode | pctl;
|
| /src/sys/dev/pci/ |
| cs428x.h | 135 uint32_t pctl; member in struct:cs428x_softc
145 uint32_t pctl; member in struct:cs428x_softc::__anon3248::__anon3249
|
| cs4280.c | 584 uint32_t pfie, pctl, pdtc; local
651 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK;
652 pctl |= sc->pctl;
653 BA1WRITE4(sc, CS4280_PCTL, pctl);
727 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL);
731 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n",
732 sc->sc_suspend_state.cs4280.pctl,
750 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK);
773 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n"
[all...] |
| /src/usr.sbin/mmcformat/ |
| uscsi_subr.c | 527 uint8_t pgcode, uint8_t pctl, void *buf, size_t len)
536 cmd[ 2] = pgcode | pctl; /* page code and control flags */
|
| /src/sys/arch/x68k/x68k/ |
| iodevice.h | 244 char pad10; unsigned char pctl; member in struct:spc
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/ |
| mt2712e.dtsi | 266 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
273 mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
