Searched refs:phy (Results 1 - 25 of 1425) sorted by relevance

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/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a-rdb.dts27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
37 phy-handle = <&mdio1_phy3>;
38 phy-connection-type = "10gbase-r";
42 phy-handle = <&mdio1_phy4>;
43 phy-connection-type = "10gbase-r";
47 phy-handle = <&mdio2_phy1>;
48 phy
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H A Dfsl-ls1088a-rdb.dts21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
34 phy-handle = <&mdio1_phy6>;
35 phy-connection-type = "qsgmii";
41 phy-handle = <&mdio1_phy7>;
42 phy-connection-type = "qsgmii";
48 phy-handle = <&mdio1_phy8>;
49 phy
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H A Dfsl-ls1046a-rdb.dts131 phy-handle = <&rgmii_phy1>;
132 phy-connection-type = "rgmii-id";
136 phy-handle = <&rgmii_phy2>;
137 phy-connection-type = "rgmii-id";
141 phy-handle = <&sgmii_phy1>;
142 phy-connection-type = "sgmii";
146 phy-handle = <&sgmii_phy2>;
147 phy-connection-type = "sgmii";
151 phy-handle = <&aqr106_phy>;
152 phy
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/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi212 phy0: ethernet-phy@0 {
215 phy1: ethernet-phy@1 {
218 phy2: ethernet-phy@2 {
221 phy3: ethernet-phy@3 {
224 phy4: ethernet-phy@4 {
227 phy5: ethernet-phy@5 {
230 phy6: ethernet-phy@6 {
233 phy7: ethernet-phy@7 {
236 phy8: ethernet-phy@8 {
239 phy9: ethernet-phy
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/src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_combo_phy.c51 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) argument
56 val = I915_READ(ICL_PORT_COMP_DW3(phy));
82 enum phy phy)
87 procmon = cnl_get_procmon_ref_values(dev_priv, phy);
89 val = I915_READ(ICL_PORT_COMP_DW1(phy));
92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
94 I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
95 I915_WRITE(ICL_PORT_COMP_DW10(phy), procmo
81 cnl_set_procmon_ref_values(struct drm_i915_private * dev_priv,enum phy phy) argument
98 check_phy_reg(struct drm_i915_private * dev_priv,enum phy phy,i915_reg_t reg,u32 mask,u32 expected_val) argument
115 cnl_verify_procmon_ref_values(struct drm_i915_private * dev_priv,enum phy phy) argument
141 enum phy phy = PHY_A; local in function:cnl_combo_phy_verify_state
187 icl_combo_phy_enabled(struct drm_i915_private * dev_priv,enum phy phy) argument
199 icl_combo_phy_verify_state(struct drm_i915_private * dev_priv,enum phy phy) argument
219 intel_combo_phy_power_up_lanes(struct drm_i915_private * dev_priv,enum phy phy,bool is_dsi,int lane_count,bool lane_reversal) argument
299 enum phy phy; local in function:icl_combo_phys_init
353 enum phy phy; local in function:icl_combo_phys_uninit
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H A Dintel_combo_phy.h14 enum phy;
19 enum phy phy, bool is_dsi,
/src/sys/dev/pci/cxgb/
H A Dcxgb_ael1002.c51 static void ael100x_txon(struct cphy *phy) argument
53 int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
56 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
60 static int ael1002_power_down(struct cphy *phy, int enable) argument
64 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);
66 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
71 static int ael1002_reset(struct cphy *phy, int wait) argument
75 if ((err = ael1002_power_down(phy, 0)) ||
76 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||
77 (err = mdio_write(phy, MDIO_DEV_PMA_PM
86 ael1002_intr_noop(struct cphy * phy) argument
91 ael100x_get_link_status(struct cphy * phy,int * link_ok,int * speed,int * duplex,int * fc) argument
144 t3_ael1002_phy_prep(struct cphy * phy,adapter_t * adapter,int phy_addr,const struct mdio_ops * mdio_ops) argument
151 ael1006_reset(struct cphy * phy,int wait) argument
156 ael1006_intr_enable(struct cphy * phy) argument
161 ael1006_intr_disable(struct cphy * phy) argument
166 ael1006_intr_clear(struct cphy * phy) argument
173 ael1006_intr_handler(struct cphy * phy) argument
183 ael1006_power_down(struct cphy * phy,int enable) argument
217 t3_ael1006_phy_prep(struct cphy * phy,adapter_t * adapter,int phy_addr,const struct mdio_ops * mdio_ops) argument
252 t3_qt2045_phy_prep(struct cphy * phy,adapter_t * adapter,int phy_addr,const struct mdio_ops * mdio_ops) argument
268 xaui_direct_reset(struct cphy * phy,int wait) argument
273 xaui_direct_get_link_status(struct cphy * phy,int * link_ok,int * speed,int * duplex,int * fc) argument
296 xaui_direct_power_down(struct cphy * phy,int enable) argument
329 t3_xaui_direct_phy_prep(struct cphy * phy,adapter_t * adapter,int phy_addr,const struct mdio_ops * mdio_ops) argument
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/src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/mscc/
H A Docelot_pcb120.dts8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
45 phy7: ethernet-phy@0 {
51 phy6: ethernet-phy@1 {
57 phy5: ethernet-phy@2 {
63 phy4: ethernet-phy@3 {
73 phy-handle = <&phy0>;
74 phy-mode = "internal";
79 phy-handle = <&phy1>;
80 phy
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/src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/cavium-octeon/
H A Dubnt_e100.dts15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
37 phy-handle = <&phy6>;
42 phy-handle = <&phy5>;
/src/sys/dev/pci/igc/
H A Digc_phy.c24 struct igc_phy_info *phy = &hw->phy; local in function:igc_init_phy_ops_generic
28 phy->ops.init_params = igc_null_ops_generic;
29 phy->ops.acquire = igc_null_ops_generic;
30 phy->ops.check_reset_block = igc_null_ops_generic;
31 phy->ops.force_speed_duplex = igc_null_ops_generic;
32 phy->ops.get_info = igc_null_ops_generic;
33 phy->ops.set_page = igc_null_set_page;
34 phy->ops.read_reg = igc_null_read_reg;
35 phy
142 struct igc_phy_info *phy = &hw->phy; local in function:igc_get_phy_id
179 struct igc_phy_info *phy = &hw->phy; local in function:igc_read_phy_reg_mdic
237 struct igc_phy_info *phy = &hw->phy; local in function:igc_write_phy_reg_mdic
292 struct igc_phy_info *phy = &hw->phy; local in function:igc_phy_setup_autoneg
470 struct igc_phy_info *phy = &hw->phy; local in function:igc_copper_link_autoneg
586 struct igc_phy_info *phy = &hw->phy; local in function:igc_check_downshift_generic
704 struct igc_phy_info *phy = &hw->phy; local in function:igc_phy_hw_reset_generic
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/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dts20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
36 phy = <&phy0>;
37 phy-mode = "10gbase-r";
43 phy = <&phy8>;
44 phy-mode = "10gbase-r";
H A Darmada-8040-db.dts52 cp0_usb3_0_phy: cp0-usb3-0-phy {
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
107 phy-names = "cp0-pcie0-x1-phy";
114 phy-names = "cp0-pcie2-x1-phy";
148 phy-names = "cp0-sata0-0-phy";
152 phy-names = "cp0-sata0-1-phy";
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/src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/
H A Djh7100-beaglev-starlight.dts16 phy-handle = <&phy>;
20 phy: ethernet-phy@7 { label
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Drk3228-evb.dts20 vcc_phy: vcc-phy-regulator {
43 phy-supply = <&vcc_phy>;
44 phy-mode = "rmii";
45 phy-handle = <&phy>;
53 phy: ethernet-phy@0 { label
54 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
58 phy
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H A Dzynq-zed.dts31 #phy-cells = <0>;
41 phy-mode = "rgmii-id";
42 phy-handle = <&ethernet_phy>;
44 ethernet_phy: ethernet-phy@0 {
46 device_type = "ethernet-phy";
61 usb-phy = <&usb_phy0>;
H A Dzynq-zybo-z7.dts35 #phy-cells = <0>;
47 phy-mode = "rgmii-id";
48 phy-handle = <&ethernet_phy>;
50 ethernet_phy: ethernet-phy@0 {
52 device_type = "ethernet-phy";
67 usb-phy = <&usb_phy0>;
H A Dzynq-zybo.dts30 #phy-cells = <0>;
42 phy-mode = "rgmii-id";
43 phy-handle = <&ethernet_phy>;
45 ethernet_phy: ethernet-phy@0 {
47 device_type = "ethernet-phy";
62 usb-phy = <&usb_phy0>;
H A Darmada-385-clearfog-gtr-l8.dts24 phy-handle = <&switch0phy0>;
30 phy-handle = <&switch0phy1>;
36 phy-handle = <&switch0phy2>;
42 phy-handle = <&switch0phy3>;
48 phy-handle = <&switch0phy4>;
54 phy-handle = <&switch0phy5>;
60 phy-handle = <&switch0phy6>;
66 phy-handle = <&switch0phy7>;
H A Dhisi-x5hd2-dkb.dts55 phy-handle = <&phy2>;
56 phy-mode = "mii";
61 phy2: ethernet-phy@2 {
69 phy-handle = <&phy1>;
70 phy-mode = "rgmii";
75 phy1: ethernet-phy@1 {
82 phy-names = "sata-phy";
H A Dsama5d3xmb_emac.dtsi13 phy-mode = "rmii";
17 phy0: ethernet-phy@1 {
/src/sys/dev/mii/
H A Dukphy_subr.c57 ukphy_status(struct mii_softc *phy) argument
59 struct mii_data *mii = phy->mii_pdata;
68 PHY_READ(phy, MII_BMSR, &bmsr);
69 PHY_READ(phy, MII_BMSR, &bmsr);
73 PHY_READ(phy, MII_BMCR, &bmcr);
95 PHY_READ(phy, MII_ANAR, &anar);
96 PHY_READ(phy, MII_ANLPAR, &anlpar);
98 if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
99 (phy->mii_extcapabilities &
101 PHY_READ(phy, MII_100T2C
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/src/sys/arch/hpcmips/vr/
H A Dvrdmaau.c96 u_int32_t phy; local in function:vrdmaau_set_aiuin
101 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
104 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAH_REG_W, phy >> 16);
105 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAL_REG_W, phy & 0xffff);
113 u_int32_t phy; local in function:vrdmaau_set_aiuout
118 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
121 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAH_REG_W, phy >> 16);
122 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAL_REG_W, phy & 0xffff);
130 u_int32_t phy; local in function:vrdmaau_set_fir
135 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
144 vrdmaau_phy_addr(struct vrdmaau_softc * sc,void * addr,u_int32_t * phy) argument
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/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-usb.dtsi17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
29 phy-names = "phy0", "phy1";
39 phy-names = "phy0", "phy1";
44 usbphy1: usb-phy@10000 {
45 compatible = "brcm,sr-usb-combo-phy";
47 #phy-cells = <1>;
51 usbphy2: usb-phy@20000 {
52 compatible = "brcm,sr-usb-hs-phy";
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/src/sys/arch/arm/sunxi/
H A Dsunxi_usb3phy.c71 { .compat = "allwinner,sun50i-h6-usb3-phy", .value = USB3PHY_H6 },
91 #define PHY_READ(phy, reg) \
92 bus_space_read_4((phy)->phy_bst, (phy)->phy_bsh, (reg))
93 #define PHY_WRITE(phy, reg, val) \
94 bus_space_write_4((phy)->phy_bst, (phy)->phy_bsh, (reg), (val))
115 struct sunxi_usb3phy * const phy = priv; local in function:sunxi_usb3phy_enable
119 val = PHY_READ(phy, SUNXI_PHY_EXTERNAL_CONTROL);
123 PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTRO
170 struct sunxi_usb3phy *phy = &sc->sc_phy; local in function:sunxi_usb3phy_attach
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/src/sys/dev/fdt/
H A Dfdt_phy.c84 struct fdtbus_phy *phy = NULL; local in function:fdtbus_phy_get_index
109 if (of_getprop_uint32(pc_phandle, "#phy-cells", &phy_cells))
118 phy = kmem_alloc(sizeof(*phy), KM_SLEEP);
119 phy->phy_pc = pc;
120 phy->phy_priv = phy_priv;
133 return phy;
142 err = fdtbus_get_index(phandle, "phy-names", phyname, &index);
150 fdtbus_phy_put(struct fdtbus_phy *phy) argument
152 struct fdtbus_phy_controller *pc = phy
159 fdtbus_phy_device(struct fdtbus_phy * phy) argument
165 fdtbus_phy_enable(struct fdtbus_phy * phy,bool enable) argument
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