| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| fsl-ls2088a-rdb.dts | 27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
37 phy-handle = <&mdio1_phy3>;
38 phy-connection-type = "10gbase-r";
42 phy-handle = <&mdio1_phy4>;
43 phy-connection-type = "10gbase-r";
47 phy-handle = <&mdio2_phy1>;
48 phy-connection-type = "10gbase-r"
[all...] |
| fsl-ls1088a-rdb.dts | 21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
34 phy-handle = <&mdio1_phy6>;
35 phy-connection-type = "qsgmii";
41 phy-handle = <&mdio1_phy7>;
42 phy-connection-type = "qsgmii";
48 phy-handle = <&mdio1_phy8>;
49 phy-connection-type = "qsgmii"
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/microchip/ |
| sparx5_pcb135_board.dtsi | 212 phy0: ethernet-phy@0 {
215 phy1: ethernet-phy@1 {
218 phy2: ethernet-phy@2 {
221 phy3: ethernet-phy@3 {
224 phy4: ethernet-phy@4 {
227 phy5: ethernet-phy@5 {
230 phy6: ethernet-phy@6 {
233 phy7: ethernet-phy@7 {
236 phy8: ethernet-phy@8 {
239 phy9: ethernet-phy@9
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_combo_phy.c | 46 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
47 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
51 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
56 val = I915_READ(ICL_PORT_COMP_DW3(phy));
82 enum phy phy)
87 procmon = cnl_get_procmon_ref_values(dev_priv, phy);
89 val = I915_READ(ICL_PORT_COMP_DW1(phy));
92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val)
141 enum phy phy = PHY_A; local in function:cnl_combo_phy_verify_state
299 enum phy phy; local in function:icl_combo_phys_init
353 enum phy phy; local in function:icl_combo_phys_uninit
[all...] |
| intel_combo_phy.h | 14 enum phy;
19 enum phy phy, bool is_dsi,
|
| /src/sys/dev/pci/cxgb/ |
| cxgb_ael1002.c | 51 static void ael100x_txon(struct cphy *phy)
53 int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
56 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
60 static int ael1002_power_down(struct cphy *phy, int enable)
64 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);
66 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
71 static int ael1002_reset(struct cphy *phy, int wait)
75 if ((err = ael1002_power_down(phy, 0)) ||
76 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||
77 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) |
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/mscc/ |
| ocelot_pcb120.dts | 8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
45 phy7: ethernet-phy@0 {
51 phy6: ethernet-phy@1 {
57 phy5: ethernet-phy@2 {
63 phy4: ethernet-phy@3 {
73 phy-handle = <&phy0>;
74 phy-mode = "internal";
79 phy-handle = <&phy1>;
80 phy-mode = "internal"
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/cavium-octeon/ |
| ubnt_e100.dts | 15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
37 phy-handle = <&phy6>;
42 phy-handle = <&phy5>;
|
| /src/sys/dev/pci/igc/ |
| igc_phy.c | 16 * igc_init_phy_ops_generic - Initialize PHY function pointers
24 struct igc_phy_info *phy = &hw->phy; local in function:igc_init_phy_ops_generic
28 phy->ops.init_params = igc_null_ops_generic;
29 phy->ops.acquire = igc_null_ops_generic;
30 phy->ops.check_reset_block = igc_null_ops_generic;
31 phy->ops.force_speed_duplex = igc_null_ops_generic;
32 phy->ops.get_info = igc_null_ops_generic;
33 phy->ops.set_page = igc_null_set_page;
34 phy->ops.read_reg = igc_null_read_reg
142 struct igc_phy_info *phy = &hw->phy; local in function:igc_get_phy_id
179 struct igc_phy_info *phy = &hw->phy; local in function:igc_read_phy_reg_mdic
237 struct igc_phy_info *phy = &hw->phy; local in function:igc_write_phy_reg_mdic
292 struct igc_phy_info *phy = &hw->phy; local in function:igc_phy_setup_autoneg
470 struct igc_phy_info *phy = &hw->phy; local in function:igc_copper_link_autoneg
586 struct igc_phy_info *phy = &hw->phy; local in function:igc_check_downshift_generic
704 struct igc_phy_info *phy = &hw->phy; local in function:igc_phy_hw_reset_generic
[all...] |
| /src/sys/arch/evbarm/conf/ |
| RPI | 134 # MII/PHY support
135 exphy* at mii? phy ? # 3Com internal PHYs
136 gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs
137 glxtphy* at mii? phy ? # Level One LXT-1000 PHYs
138 gphyter* at mii? phy ? # NS83861 Gig-E PHY
139 icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x
140 igphy* at mii? phy ? # Intel IGP01E1000
141 ihphy* at mii? phy ? # Intel 82577 PHYs
142 ikphy* at mii? phy ? # Intel 82563 PHY
[all...] |
| ARMADAXP | 270 acphy* at mii? phy ? # Altima AC101 10/100 PHY
271 amhphy* at mii? phy ? # AMD 79c901 PHY (10BASE-T part)
272 bmtphy* at mii? phy ? # Broadcom BCM5201/5202 PHYs
273 brgphy* at mii? phy ? # Broadcom BCM5400/5401 Gig-E PHYs
274 ciphy* at mii? phy ? # Cicada CS8201 Gig-E PHYs
275 dmphy* at mii? phy ? # Davicom DM9101 PHYs
276 exphy* at mii? phy ? # 3Com internal PHYs
277 gentbi* at mii? phy ? # Generic ten-bit 1000BASE-X PHY
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| sun8i-h3-nanopi-neo.dts | 55 phy-handle = <&int_mii_phy>;
56 phy-mode = "mii";
|
| sun8i-h3-orangepi-plus2e.dts | 45 * with 2G RAM and an external gbit ethernet phy.
68 phy-supply = <®_gmac_3v3>;
69 phy-handle = <&ext_rgmii_phy>;
70 phy-mode = "rgmii-id";
75 ext_rgmii_phy: ethernet-phy@1 {
76 compatible = "ethernet-phy-ieee802.3-c22";
|
| sun8i-h3-zeropi.dts | 65 ext_rgmii_phy: ethernet-phy@7 {
66 compatible = "ethernet-phy-ieee802.3-c22";
74 phy-supply = <®_gmac_3v3>;
75 phy-handle = <&ext_rgmii_phy>;
76 phy-mode = "rgmii-id";
|
| rk3228-evb.dts | 20 vcc_phy: vcc-phy-regulator {
43 phy-supply = <&vcc_phy>;
44 phy-mode = "rmii";
45 phy-handle = <&phy>;
53 phy: ethernet-phy@0 { label
54 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
58 phy-is-integrated
[all...] |
| artpec6-devboard.dts | 56 phy-handle = <&phy1>;
57 phy-mode = "gmii";
63 phy1: phy@0 {
64 compatible = "ethernet-phy-ieee802.3-c22";
65 device_type = "ethernet-phy";
|
| sun6i-a31s-cs908.dts | 70 phy-handle = <&phy1>;
71 phy-mode = "mii";
82 phy1: ethernet-phy@1 {
|
| zynq-zed.dts | 31 #phy-cells = <0>;
41 phy-mode = "rgmii-id";
42 phy-handle = <ðernet_phy>;
44 ethernet_phy: ethernet-phy@0 {
46 device_type = "ethernet-phy";
61 usb-phy = <&usb_phy0>;
|
| zynq-zybo-z7.dts | 35 #phy-cells = <0>;
47 phy-mode = "rgmii-id";
48 phy-handle = <ðernet_phy>;
50 ethernet_phy: ethernet-phy@0 {
52 device_type = "ethernet-phy";
67 usb-phy = <&usb_phy0>;
|
| zynq-zybo.dts | 30 #phy-cells = <0>;
42 phy-mode = "rgmii-id";
43 phy-handle = <ðernet_phy>;
45 ethernet_phy: ethernet-phy@0 {
47 device_type = "ethernet-phy";
62 usb-phy = <&usb_phy0>;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/ |
| armada-8040-mcbin.dts | 20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
35 /* Network PHY */
36 phy = <&phy0>;
37 phy-mode = "10gbase-r";
42 /* Network PHY */
43 phy = <&phy8>;
44 phy-mode = "10gbase-r"
[all...] |
| armada-8040-db.dts | 52 cp0_usb3_0_phy: cp0-usb3-0-phy {
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
107 phy-names = "cp0-pcie0-x1-phy";
114 phy-names = "cp0-pcie2-x1-phy";
148 phy-names = "cp0-sata0-0-phy";
152 phy-names = "cp0-sata0-1-phy";
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| bcm958742t.dts | 43 enet-phy-lane-swap;
|
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/ |
| jh7100-beaglev-starlight.dts | 16 phy-handle = <&phy>;
20 phy: ethernet-phy@7 { label
|
| /src/sys/dev/mii/ |
| ukphy_subr.c | 34 * Subroutines shared by the ukphy driver and other PHY drivers.
53 * Media status subroutine. If a PHY driver does media detection simply
57 ukphy_status(struct mii_softc *phy)
59 struct mii_data *mii = phy->mii_pdata;
68 PHY_READ(phy, MII_BMSR, &bmsr);
69 PHY_READ(phy, MII_BMSR, &bmsr);
73 PHY_READ(phy, MII_BMCR, &bmcr);
95 PHY_READ(phy, MII_ANAR, &anar);
96 PHY_READ(phy, MII_ANLPAR, &anlpar);
98 if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &
[all...] |
