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    Searched refs:phyclk_khz (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr.c 168 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz
173 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
174 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/
amdgpu_dce120_clk_mgr.c 117 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) {
120 clk_mgr_base->clks.phyclk_khz = max_pix_clk;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 191 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
192 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
194 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
286 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
287 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
414 else if (a->phyclk_khz != b->phyclk_khz
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr.c 143 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
144 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
145 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 782 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) {
785 clk_mgr->clks.phyclk_khz = max_pix_clk;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc.h 284 int phyclk_khz; member in struct:dc_clocks
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 1151 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1392 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 2656 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2689 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc.c 2701 info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;

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