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    Searched refs:pic_height (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
dsc.h 41 uint32_t pic_height; member in struct:dsc_config
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dsc.h 114 * @pic_height: Vertical height of the input display frame
116 u16 pic_height; member in struct:drm_dsc_config
339 * @pic_height:
340 * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
343 __be16 pic_height; member in struct:drm_dsc_picture_parameter_set
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dsc.c 293 DC_LOG_DSC("\tpic_height %d", pps->pic_height);
343 ASSERT(dsc_cfg->pic_height);
353 !dsc_cfg->pic_width || !dsc_cfg->pic_height ||
372 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
381 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
383 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
384 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
385 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
501 reg_vals->pps.pic_height = 0
    [all...]
amdgpu_dcn20_resource.c 2306 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
amdgpu_dc_dsc.c 578 int pic_height; local in function:setup_dsc_config
586 pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
742 slice_height = min(policy.min_slice_height, pic_height);
744 slice_height = min(min_slice_height_override, pic_height);
746 while (slice_height < pic_height && (pic_height % slice_height != 0 ||
750 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) // For the case when pic_height < dsc_policy.min_sice_height
756 dsc_cfg->num_slices_v = pic_height/slice_height;
amdgpu_rc_calc_dpi.c 48 to->pic_height = from->pic_height;
  /src/sys/external/bsd/drm2/dist/drm/
drm_dsc.c 119 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 434 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
538 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_vdsc.c 396 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
563 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
750 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
icl_dsi.c 1369 WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
intel_dp.c 2075 * with that if pic_height is an integral multiple of 8. Eventually add
2078 if (vdsc_cfg->pic_height % 8 == 0)
2080 else if (vdsc_cfg->pic_height % 4 == 0)
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 11799 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)

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