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    Searched refs:pic_width (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
dsc.h 40 uint32_t pic_width; member in struct:dsc_config
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
amdgpu_dc_dsc.c 572 int pic_width; local in function:setup_dsc_config
585 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
591 if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width)
676 if (pic_width % max_slices_h == 0)
686 min_slices_h = pic_width / dsc_common_caps.max_slice_width;
687 if (pic_width % dsc_common_caps.max_slice_width)
700 if (pic_width % min_slices_h != 0)
733 slice_width = pic_width / num_slices_h;
amdgpu_rc_calc_dpi.c 47 to->pic_width = from->pic_width;
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dsc.h 110 * @pic_width: Width of the input display frame in pixels
112 u16 pic_width; member in struct:drm_dsc_config
345 * @pic_width:
346 * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
349 __be16 pic_width; member in struct:drm_dsc_picture_parameter_set
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dsc.c 173 if (dsc_cfg->pic_width > dsc20->max_image_width)
294 DC_LOG_DSC("\tpic_width %d", pps->pic_width);
342 ASSERT(dsc_cfg->pic_width);
353 !dsc_cfg->pic_width || !dsc_cfg->pic_height ||
371 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
379 // see what happens when the same condition doesn't apply for slice_width/pic_width.
380 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
500 reg_vals->pps.pic_width = 0;
559 PIC_WIDTH, reg_vals->pps.pic_width
    [all...]
amdgpu_dcn20_resource.c 2304 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
  /src/sys/external/bsd/drm2/dist/drm/
drm_dsc.c 122 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 433 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
450 dsc_cfg.pic_width *= opp_cnt;
537 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_vdsc.c 395 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
397 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
564 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
748 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
icl_dsi.c 1367 WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 11798 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)

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