| /src/sys/arch/sparc64/sparc64/ |
| intr.c | 230 ("%s: level %x ivec %x inumber %x pil %x\n",
249 printf("\nintr_establish: NULL vector fun %p arg %p pil %p\n",
279 printf("\nintr_establish: vector %x pil %x mapintr %p "
296 sparc_softintr_establish(int pil, int (*fun)(void *), void *arg)
302 ih->ih_pil = pil;
333 int pil; local in function:softint_init_md
337 pil = IPL_SOFTBIO;
340 pil = IPL_SOFTNET;
343 pil = IPL_SOFTSERIAL;
346 pil = IPL_SOFTCLOCK
[all...] |
| clock.c | 360 tickintr_establish(int pil, int (*fun)(void *))
366 ih = sparc_softintr_establish(pil, fun, NULL);
369 intr_establish(pil, true, ih);
381 stickintr_establish(int pil, int (*fun)(void *))
387 ih = sparc_softintr_establish(pil, fun, NULL);
390 intr_establish(pil, true, ih);
404 stick2eintr_establish(int pil, int (*fun)(void *))
410 ih = sparc_softintr_establish(pil, fun, NULL);
413 intr_establish(pil, true, ih);
|
| locore.s | 1287 wrpr g0, 15, %pil /* t1 = splhigh() */
1830 * We will assume that %pil is not lost so we won't bother to save it
1991 wrpr %g0, 15, %pil ! Disable interrupts, too
2461 * We will assume that %pil is not lost so we won't bother to save it
2518 rdpr %pil, %g4
2602 * We will assume that %pil is not lost so we won't bother to save it
2705 * We will assume that %pil is not lost so we won't bother to save it
2760 rdpr %pil, %g4
2990 rdpr %pil, %g5
3219 rdpr %pil, %g
[all...] |
| machdep.c | 2378 sparc_mainbus_intr_establish(bus_space_tag_t t, int pil, int level,
2386 intr_establish(pil, level != IPL_VM, ih);
|
| /src/sys/arch/sparc/sparc/ |
| intr.c | 707 panic("intr_establish: class lvl (%d) < pil (%d)\n",
710 /* pre-shift to PIL field in %psr */
743 int sic_pil; /* Actual machine PIL that is used */
770 int pil; local in function:sparc_softintr_establish
783 pil = pilreq = level;
787 pil = 1;
790 pil = 4;
793 pil = 6;
799 sic->sic_pil = pil;
819 * pre-shift to PIL field in %ps
[all...] |
| pci_machdep.c | 518 int pil; local in function:pci_intr_string
520 pil = mspcic_assigned_interrupt(ih);
521 snprintf(buf, len, "line %d (pil %d)", ih, pil);
562 * pil the handler was established for, but we don't need to
|
| msiiep.c | 387 * Get the PIL currently assigned for this interrupt input line.
558 * for ms-IIep. The PIL for each line is programmable via pcic interrupt
567 int pil; local in function:mspcic_intr_establish
571 /* use pil set-up by prom */
572 pil = mspcic_assigned_interrupt(line);
573 if (pil == -1)
578 intr_establish(pil, ipl, ih, fastvec, false);
|
| cpu.c | 729 u_int pil; local in function:xcall
759 pil = (getpsr() & PSR_PIL) >> 8;
761 if (cold || pil <= IPL_SCHED)
775 cpu_number(), func, pil, pc);
814 raise_ipi(cpi,13+fasttrap);/*xcall_cookie->pil*/
|
| machdep.c | 3018 sparc_mainbus_intr_establish(bus_space_tag_t t, int pil, int level,
3027 intr_establish(pil, level, ih, fastvec, false);
|
| /src/sys/arch/sparc/dev/ |
| sbus.c | 580 int pil; local in function:sbus_intr_establish
588 pil = pri & ~SBUS_INTR_COMPAT;
590 pil = sc->sc_intr2ipl[pri];
594 intr_establish(pil, level, ih, fastvec, false);
|
| vme_machdep.c | 753 int pil; local in function:sparc_vme_intr_establish
756 pil = vme_ipl_to_pil[svih->pri];
758 if (level < pil)
759 panic("vme_intr_establish: class lvl (%d) < pil (%d)\n",
760 level, pil);
769 for (ih = intrhand[pil]; ih != NULL; ih = ih->ih_next)
777 intr_establish(pil, 0, ih, NULL, false);
|
| /src/sys/dev/pci/ |
| pccbb.c | 1100 struct pccbb_intrhand_list *pil; local in function:pccbbintr_function
1103 LIST_FOREACH(pil, &sc->sc_pil, pil_next) {
1104 s = splraiseipl(pil->pil_icookie);
1105 val = (*pil->pil_func)(pil->pil_arg);
1709 struct pccbb_intrhand_list *pil, *newpil; local in function:pccbb_intr_establish
1732 for (pil = LIST_FIRST(&sc->sc_pil);
1733 LIST_NEXT(pil, pil_next) != NULL;
1734 pil = LIST_NEXT(pil, pil_next))
1757 struct pccbb_intrhand_list *pil; local in function:pccbb_intr_disestablish
[all...] |
| /src/sys/arch/sparc64/include/ |
| psl.h | 53 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
426 * GCC pseudo-functions for manipulating PIL
445 __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
447 __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory"); \
455 __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
459 __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory"); \
469 __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
470 __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory"); \
478 __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
481 __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory");
553 int pil; variable in typeref:typename:int
[all...] |
| /src/sys/arch/sun68k/sun68k/ |
| bus.c | 693 sun68k_mainbus_intr_establish(bus_space_tag_t t, int pil, int level, int flags,
697 isr_add_autovect(handler, arg, pil);
|
| /src/sys/arch/sparc/stand/ofwboot/ |
| srt0.s | 101 wrpr %g0, 0, %pil ! So I lied
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| qcom-sdx55.dtsi | 500 pil-reloc@94c {
501 compatible = "qcom,pil-reloc-info";
|
| qcom-apq8064-sony-xperia-yuga.dts | 395 riva-pil@3204000 {
|
| qcom-msm8974.dtsi | 344 adsp-pil {
345 compatible = "qcom,msm8974-adsp-pil";
839 compatible = "qcom,msm8974-mss-pil";
888 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
|
| qcom-msm8974-samsung-klte.dts | 319 adsp-pil {
|
| qcom-apq8064.dtsi | 1511 riva: riva-pil@3204000 {
1512 compatible = "qcom,riva-pil";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| msm8916.dtsi | 1310 compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1727 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
|
| ipq6018.dtsi | 579 compatible = "qcom,ipq6018-wcss-pil";
|
| sc7180-idp.dts | 371 compatible = "qcom,sc7180-mss-pil";
|
| qcs404.dtsi | 1109 pil-reloc@94c {
1110 compatible = "qcom,pil-reloc-info";
|
| msm8994-msft-lumia-octagon.dtsi | 239 * The region reserved for pil is 0x7000000-0xef00000
|
