| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 138 for (i = 0; i < pool->pipe_count; i++) {
208 for (i = 0; i < pool->pipe_count; i++) {
253 for (i = 0; i < pool->pipe_count; i++) {
307 for (i = 0; i < pool->pipe_count; i++) {
346 for (i = 0; i < pool->pipe_count; i++) {
399 for (i = 0; i < pool->pipe_count; i++) {
514 for (i = 0; i < pool->pipe_count; i++) {
|
| amdgpu_dcn10_hw_sequencer.c | 98 for (i = 0; i < dc->res_pool->pipe_count; i++) {
167 for (i = 0; i < pool->pipe_count; i++) {
199 for (i = 0; i < pool->pipe_count; i++) {
224 for (i = 0; i < pool->pipe_count; i++) {
256 for (i = 0; i < pool->pipe_count; i++) {
289 for (i = 0; i < pool->pipe_count; i++) {
331 for (i = 0; i < pool->pipe_count; i++) {
691 for (i = 0; i < dc->res_pool->pipe_count; i++) {
735 for (i = 0; i < dc->res_pool->pipe_count; i++) {
761 for (i = 0; i < dc->res_pool->pipe_count; i++)
[all...] |
| amdgpu_dcn10_resource.c | 950 for (i = 0; i < pool->base.pipe_count; i++) {
1344 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1347 pool->base.pipe_count = 3;
1493 for (i = 0; i < pool->base.pipe_count; i++) {
1562 pool->base.pipe_count = j;
1568 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1569 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1591 dc->caps.max_planes = pool->base.pipe_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 794 for (i = 0; i < pool->base.pipe_count; i++) {
957 dc->res_pool->pipe_count,
1244 pool->opps[pool->pipe_count] = &dce110_oppv->base;
1245 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1246 pool->mis[pool->pipe_count] = &dce110_miv->base;
1247 pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1248 pool->pipe_count++;
1341 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1342 pool->base.underlay_pipe_index = pool->base.pipe_count;
1414 for (i = 0; i < pool->base.pipe_count; i++)
[all...] |
| amdgpu_dce110_hw_sequencer.c | 1508 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1802 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1818 if (i == dc->res_pool->pipe_count)
1965 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1992 if (i == dc->res_pool->pipe_count) {
1993 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2042 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2067 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2369 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2397 for (i = 0; i < dc->res_pool->pipe_count; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_resource.c | 785 for (i = 0; i < pool->base.pipe_count; i++) {
858 for (i = 0; i < dc->res_pool->pipe_count; i++) {
943 pool->base.pipe_count = res_cap.num_timing_generator;
1022 for (i = 0; i < pool->base.pipe_count; i++) {
1084 dc->caps.max_planes = pool->base.pipe_count;
1141 pool->base.pipe_count = res_cap_81.num_timing_generator;
1219 for (i = 0; i < pool->base.pipe_count; i++) {
1281 dc->caps.max_planes = pool->base.pipe_count;
1338 pool->base.pipe_count = res_cap_83.num_timing_generator;
1412 for (i = 0; i < pool->base.pipe_count; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 1338 for (i = 0; i < pool->base.pipe_count; i++) {
1590 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1837 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1892 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1908 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2244 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2290 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2358 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2381 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2403 for (i = 0; i < dc->res_pool->pipe_count; i++)
3070 uint32_t pipe_count = pool->res_cap->num_dwb; local in function:dcn20_dwbc_create
3093 uint32_t pipe_count = pool->res_cap->num_dwb; local in function:dcn20_mmhubbub_create
[all...] |
| amdgpu_dcn20_hwseq.c | 1372 int opp_count = dc->res_pool->pipe_count;
1566 for (i = 0; i < dc->res_pool->pipe_count; i++)
1572 for (i = 0; i < dc->res_pool->pipe_count; i++)
1575 for (i = 0; i < dc->res_pool->pipe_count; i++)
1588 for (i = 0; i < dc->res_pool->pipe_count; i++)
1596 for (i = 0; i < dc->res_pool->pipe_count; i++)
1607 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1625 for (i = 0; i < dc->res_pool->pipe_count; i++)
1635 for (i = 0; i < dc->res_pool->pipe_count; i++)
1645 for (i = 0; i < dc->res_pool->pipe_count; i++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 780 for (i = 0; i < dc->res_pool->pipe_count; i++) {
856 full_pipe_count = dc->res_pool->pipe_count;
925 int pipe_count = dc->res_pool->pipe_count; local in function:enable_timing_multisync
928 for (i = 0; i < pipe_count; i++) {
951 int pipe_count = dc->res_pool->pipe_count; local in function:program_timing_sync
954 for (i = 0; i < pipe_count; i++) {
961 for (i = 0; i < pipe_count; i++) {
974 for (j = i + 1; j < pipe_count; j++)
[all...] |
| amdgpu_dc_surface.c | 160 for (i = 0; i < dc->res_pool->pipe_count; i++) {
172 for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
| amdgpu_dc_debug.c | 323 for (i = 0; i < dc->res_pool->pipe_count; i++) {
335 for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
| amdgpu_dc_resource.c | 1135 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1147 for (i = pool->pipe_count - 1; i >= 0; i--) {
1205 for (i = pool->pipe_count - 1; i >= 0; i--) {
1231 for (i = 0; i < pool->pipe_count; i++) {
1360 for (i = pool->pipe_count - 1; i >= 0; i--) {
1642 for (i = 0; i < pool->pipe_count; i++) {
2110 for (j = 0; j < dc->res_pool->pipe_count; j++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 893 for (i = 0; i < pool->base.pipe_count; i++) {
1060 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1139 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1346 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1635 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1690 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1707 pool->base.pipe_count = 4;
1799 for (i = 0; i < pool->base.pipe_count; i++) {
1867 pool->base.pipe_count = j;
1911 dc->caps.max_planes = pool->base.pipe_count;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 737 for (i = 0; i < pool->base.pipe_count; i++) {
824 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1044 pool->base.pipe_count = res_cap.num_timing_generator;
1053 for (i = 0; i < pool->base.pipe_count; i++) {
1116 dc->caps.max_planes = pool->base.pipe_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 599 for (i = 0; i < pool->base.pipe_count; i++) {
1051 pool->base.pipe_count = res_cap.num_timing_generator;
1138 for (i = 0; i < pool->base.pipe_count; i++) {
1214 pool->base.pipe_count = j;
1229 dc->caps.max_planes = pool->base.pipe_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr.c | 106 for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 187 unsigned int pipe_count; member in struct:resource_pool
|
| dce_calcs.h | 487 int pipe_count,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 755 for (i = 0; i < pool->base.pipe_count; i++) {
878 dc->res_pool->pipe_count,
1210 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1295 for (i = 0; i < pool->base.pipe_count; i++) {
1364 dc->caps.max_planes = pool->base.pipe_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 114 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dce_calcs.c | 2765 const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)
2781 for (i = 0; i < pipe_count; i++) {
2891 for (i = 0; i < pipe_count; i++) {
2987 int pipe_count)
2992 for (i = 0; i < pipe_count; i++) {
3023 int pipe_count,
3031 populate_initial_data(pipe, pipe_count, data);
3034 calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
|
| amdgpu_dcn_calcs.c | 867 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1173 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
|
