| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| display_rq_dlg_calc_20.h | 60 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
69 const unsigned int pipe_idx,
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| display_rq_dlg_calc_20v2.h | 60 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
69 const unsigned int pipe_idx,
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| amdgpu_display_rq_dlg_calc_20.c | 54 const unsigned int pipe_idx,
774 const unsigned int pipe_idx,
782 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
783 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
784 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
785 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
786 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
787 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
932 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1020 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
[all...] |
| amdgpu_display_rq_dlg_calc_20v2.c | 54 const unsigned int pipe_idx,
774 const unsigned int pipe_idx,
782 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
783 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
784 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
785 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
786 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
787 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
932 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1021 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| display_rq_dlg_calc_21.h | 59 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
68 const unsigned int pipe_idx,
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| amdgpu_display_rq_dlg_calc_21.c | 820 const unsigned int pipe_idx,
828 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
829 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
830 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
831 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
832 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
833 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
978 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1060 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1109 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_lib.h | 51 const unsigned int pipe_idx,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 1543 int pipe_idx)
1551 *dsc = pool->dscs[pipe_idx];
1552 res_ctx->is_dsc_acquired[pipe_idx] = true;
1732 int pipe_idx = next_odm_pipe->pipe_idx; local in function:dcn20_split_stream_for_odm
1736 next_odm_pipe->pipe_idx = pipe_idx;
1737 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1738 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1739 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1805 int pipe_idx = secondary_pipe->pipe_idx; local in function:dcn20_split_stream_for_mpc
2461 int i, pipe_idx, vlevel_split; local in function:dcn20_validate_apply_pipe_split_flags
2556 int pipe_cnt, i, pipe_idx, vlevel; local in function:dcn20_fast_validate_bw
2667 int pipe_cnt, i, pipe_idx; local in function:dcn20_calculate_wm
2781 int i, j, pipe_idx, pipe_idx_unsplit; local in function:dcn20_calculate_dlg_params
[all...] |
| amdgpu_dcn20_hwseq.c | 604 pipe_ctx->pipe_idx);
1049 pipe_ctx->pipe_idx,
1066 pipe_ctx->pipe_idx,
1207 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1600 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
2081 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2135 *color = pipe_colors[top_pipe->pipe_idx];
2357 pipe_ctx->pipe_idx = i;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_resource.c | 1135 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1138 secondary_pipe->pipe_idx = preferred_pipe_idx;
1150 secondary_pipe->pipe_idx = i;
1250 split_pipe->pipe_idx = i;
1306 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); local in function:dc_add_plane_to_context
1307 if (pipe_idx >= 0)
1308 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1655 pipe_ctx->pipe_idx = i;
1945 pipe_ctx->pipe_idx = tg_inst;
1963 int pipe_idx = -1 local in function:resource_map_pool_resources
[all...] |
| amdgpu_dc_debug.c | 328 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
338 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
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| amdgpu_dc.c | 1345 context->res_ctx.pipe_ctx[i].pipe_idx = i;
1388 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1391 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1394 cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1397 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
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| amdgpu_dc_link.c | 2746 pipe_ctx->pipe_idx);
2836 pipe_ctx->pipe_idx);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 153 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
245 pp_display_cfg->disp_configs[0].pipe_idx;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 128 uint8_t pipe_idx; member in struct:dm_pp_single_disp_config
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 1051 int pipe_cnt, i, pipe_idx; local in function:dcn21_calculate_wm
1060 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1069 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1070 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1072 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1075 pipe_idx++;
1088 if (pipe_cnt != pipe_idx) {
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 1277 pipe_ctx[pipe_ctx->pipe_idx];
1514 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1784 uint32_t *pipe_idx)
1811 if (pipe_ctx->pipe_idx != underlay_idx) {
1812 *pipe_idx = i;
1850 uint32_t pipe_idx = 0; local in function:enable_fbc
1852 if (should_enable_fbc(dc, context, &pipe_idx)) {
1856 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2536 pipe_ctx->pipe_idx,
2557 pipe_ctx->pipe_idx,
[all...] |
| amdgpu_dce110_resource.c | 909 if (pipe_ctx->pipe_idx != underlay_idx)
1118 pipe_ctx->pipe_idx = underlay_idx;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 289 uint8_t pipe_idx; member in struct:pipe_ctx
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 517 int pipe_idx = secondary_pipe->pipe_idx; local in function:split_stream_across_pipes
524 secondary_pipe->pipe_idx = pipe_idx;
525 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
526 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
527 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
528 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
529 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
530 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_resource.c | 1154 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1155 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1156 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1157 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
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| amdgpu_dcn10_hw_sequencer.c | 925 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
1129 pipe_ctx->pipe_idx);
1211 pipe_ctx->pipe_idx = i;
1709 pipe_ctx->pipe_idx,
1741 pipe_ctx->pipe_idx,
1800 pipe_ctx->pipe_idx,
1927 pipe_ctx->pipe_idx,
1944 pipe_ctx->pipe_idx,
2582 old_pipe_ctx->pipe_idx);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 525 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
665 pp_display_cfg->disp_configs[0].pipe_idx;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_pp_smu.c | 107 adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
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