| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_resource.h | 152 int *pipe_split_from,
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| amdgpu_dcn20_resource.c | 2551 int *pipe_split_from,
2582 pipe_split_from[i] = -1;
2588 if (!pipe->stream || pipe_split_from[i] >= 0)
2600 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2634 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2664 int *pipe_split_from,
2676 if (pipe_split_from[i] < 0) {
2687 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2688 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]
2887 int pipe_split_from[MAX_PIPES]; local in function:dcn20_validate_bandwidth_internal
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 1048 int *pipe_split_from,
1067 if (pipe_split_from[i] < 0) {
1078 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1079 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1081 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1137 int pipe_split_from[MAX_PIPES]; local in function:dcn21_validate_bandwidth
1144 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1159 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
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