HomeSort by: relevance | last modified time | path
    Searched refs:pipestat (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm/dist/shared-core/
i915_irq.c 39 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
41 * PIPESTAT alone.
90 if ((dev_priv->pipestat[pipe] & mask) != mask) {
93 dev_priv->pipestat[pipe] |= mask;
95 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
103 if ((dev_priv->pipestat[pipe] & mask) != 0) {
106 dev_priv->pipestat[pipe] &= ~mask;
107 I915_WRITE(reg, dev_priv->pipestat[pipe]);
383 u32 pipestat; local in function:i915_enable_vblank
390 pipestat = PIPE_START_VBLANK_INTERRUPT_ENABLE
    [all...]
i915_drv.h 136 u32 pipestat[2]; member in struct:drm_i915_private

Completed in 123 milliseconds