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    Searched refs:pix_clk_params (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_clock_source.c 402 struct pixel_clk_params *pix_clk_params,
410 switch (pix_clk_params->signal_type) {
412 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
413 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
414 switch (pix_clk_params->color_depth) {
435 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
436 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
440 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
441 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
447 encoder_object_id = pix_clk_params->encoder_object_id
    [all...]
dce_clk_mgr.c 204 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
205 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
211 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
212 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
amdgpu_dce_clk_mgr.c 185 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
186 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
192 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
193 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 237 struct pixel_clk_params pix_clk_params; member in struct:stream_resource
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 121 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
125 &pipes[i].stream_res.pix_clk_params,
amdgpu_dc_link.c 1518 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 1154 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1157 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1163 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1167 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1297 &pipe_ctx->stream_res.pix_clk_params,
amdgpu_dce110_resource.c 897 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
900 &pipe_ctx->stream_res.pix_clk_params,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer_debug.c 437 pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
amdgpu_dcn10_resource.c 1067 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1071 &pipe_ctx->stream_res.pix_clk_params,
amdgpu_dcn10_hw_sequencer.c 802 &pipe_ctx->stream_res.pix_clk_params,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1491 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1495 &pipe_ctx->stream_res.pix_clk_params,
amdgpu_dcn20_hwseq.c 647 &pipe_ctx->stream_res.pix_clk_params,

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