| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/ |
| amdgpu_dce120_clk_mgr.c | 42 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
44 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
46 { .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
48 { .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
50 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 58 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
60 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
62 { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
64 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
66 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
70 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
72 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
74 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
76 { .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
78 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }
[all...] |
| amdgpu_dce_clock_source.c | 993 unsigned int *pixel_clk_khz)
1005 *pixel_clk_khz = clock_hz / 100;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 61 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
63 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
65 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
67 { .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
69 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/ |
| amdgpu_dce112_clk_mgr.c | 63 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
65 { .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
67 { .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
69 { .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
71 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 74 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
76 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
78 { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
80 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
82 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
216 clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| clock_source.h | 174 unsigned int *pixel_clk_khz);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr_internal.h | 194 int pixel_clk_khz; member in struct:state_dependent_clocks
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 393 unsigned int pixel_clk_khz; member in struct:dc_cursor_mi_param
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hubp.c | 1173 dst_x_offset /= param->pixel_clk_khz;
|
| amdgpu_dcn10_hw_sequencer.c | 2952 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 987 dst_x_offset /= param->pixel_clk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 2682 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
|
