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    Searched refs:plane_res (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 544 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
659 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
661 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
665 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
667 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
669 pipe_ctx->plane_res.scl_data.recout.width =
671 - pipe_ctx->plane_res.scl_data.recout.x;
673 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
675 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.
    [all...]
amdgpu_dc_stream.c 349 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
351 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
352 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
638 hubp = pipe_ctx->plane_res.hubp;
amdgpu_dc.c 466 if (pipes->plane_res.xfm &&
467 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
468 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
469 pipes->plane_res.xfm,
470 pipes->plane_res.scl_data.lb_params.depth,
2266 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2267 cur_pipe.plane_res.hubp, dc->ctx,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 281 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
609 struct transform *xfm = pipe_ctx->plane_res.xfm;
1199 switch (pipe_ctx->plane_res.scl_data.format) {
1236 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1247 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1248 pipe_ctx->plane_res.xfm,
1249 pipe_ctx->plane_res.scl_data.lb_params.depth,
1266 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1267 &pipe_ctx->plane_res.scl_data)
    [all...]
amdgpu_dce110_resource.c 1114 pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
1115 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
1116 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
1150 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 181 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
182 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
183 pipe_ctx->plane_res.hubp, flip_immediate);
268 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
269 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
270 pipe_ctx->plane_res.hubp,
562 struct hubp *hubp = pipe_ctx->plane_res.hubp;
563 struct dpp *dpp = pipe_ctx->plane_res.dpp;
582 pipe_ctx->plane_res.dpp
    [all...]
amdgpu_dcn20_resource.c 1737 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1738 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1739 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1740 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1741 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1742 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1753 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1770 sd = &next_odm_pipe->plane_res.scl_data;
1812 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1813 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dmub_psr.c 122 !&pipe_ctx->plane_res ||
144 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
146 if (pipe_ctx->plane_res.hubp)
147 copy_settings_data->hubp_inst = pipe_ctx->plane_res.hubp->inst;
150 if (pipe_ctx->plane_res.dpp)
151 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 315 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
330 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
338 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;
339 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;
340 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;
341 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;
389 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
390 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
391 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
392 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0
    [all...]
amdgpu_dce_calcs.c 2804 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2806 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2807 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2808 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2809 data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2810 data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2858 data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
2859 data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
2862 data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
2863 data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 468 struct hubp *hubp = pipe_ctx->plane_res.hubp;
941 hubp = pipe_ctx->plane_res.hubp;
966 hubp = pipe_ctx->plane_res.hubp;
979 hubp = pipe_ctx->plane_res.hubp;
989 hubp = pipe_ctx->plane_res.hubp;
1001 hubp = pipe_ctx->plane_res.hubp;
1033 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1034 int dpp_id = pipe_ctx->plane_res.dpp->inst;
1049 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1086 struct hubp *hubp = pipe_ctx->plane_res.hubp
    [all...]
amdgpu_dcn10_resource.c 1154 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1155 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1156 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1157 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr.c 112 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
113 pipe_ctx->plane_res.dpp,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 282 struct plane_resource plane_res; member in struct:pipe_ctx
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 121 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
123 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

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