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  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 1553 temp |= pll->state.hw_state.pll0;
1686 hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1687 hw_state->pll0 &= PORT_PLL_M2_MASK;
1850 dpll_hw_state->pll0 = clk_div->m2_int;
1932 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1936 hw_state->pll0,
intel_ddi.c 1725 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
intel_display.c 13679 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);

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