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  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
stih407-clock.dtsi 75 compatible = "st,clkgen-pll0-a0";
102 clk_s_c0_pll0: clk-s-c0-pll0 {
104 compatible = "st,clkgen-pll0-c0";
stih410-clock.dtsi 75 compatible = "st,clkgen-pll0-a0";
102 clk_s_c0_pll0: clk-s-c0-pll0 {
104 compatible = "st,clkgen-pll0-c0";
stih418-clock.dtsi 76 compatible = "st,clkgen-pll0-a0";
103 clk_s_c0_pll0: clk-s-c0-pll0 {
105 compatible = "st,clkgen-pll0-c0";
dove-cubox.dts 101 /* connect xtal input as source of pll0 and pll1 */
da850.dtsi 135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";
r8a73a4.dtsi 484 clock-output-names = "main", "pll0", "pll1", "pll2",
sh73a0.dtsi 651 clock-output-names = "main", "pll0", "pll1", "pll2",
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 1553 temp |= pll->state.hw_state.pll0;
1686 hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1687 hw_state->pll0 &= PORT_PLL_M2_MASK;
1850 dpll_hw_state->pll0 = clk_div->m2_int;
1932 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1936 hw_state->pll0,
intel_ddi.c 1725 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
intel_display.c 13679 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
k3-j721e-main.dtsi 368 wiz0_pll0_refclk: pll0-refclk {
428 wiz1_pll0_refclk: pll0-refclk {
488 wiz2_pll0_refclk: pll0-refclk {
548 wiz3_pll0_refclk: pll0-refclk {
k3-j7200-main.dtsi 549 wiz0_pll0_refclk: pll0-refclk {

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