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    Searched refs:pll3 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/arch/hpcmips/dev/
mq200priv.h 46 int pll1, pll2, pll3; member in struct:mq200_clock_setting
mq200subr.c 241 mq200_set_pll(sc, MQ200_CLOCK_PLL3, clock->pll3);
335 if (clock->pll3 == 0) {
336 DPRINTF("PLL3 disable\n");
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 1571 temp |= pll->state.hw_state.pll3;
1695 hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1696 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1855 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
1932 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1939 hw_state->pll3,
intel_ddi.c 1726 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
intel_display.c 13682 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
sh73a0.dtsi 652 "pll3", "dsi0phy", "dsi1phy",

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