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  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 1585 temp |= pll->state.hw_state.pll8;
1703 hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1704 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1860 dpll_hw_state->pll8 = targ_cnt;
1933 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
1941 hw_state->pll8,
intel_display.c 13684 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);

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