HomeSort by: relevance | last modified time | path
    Searched refs:pll9 (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.h 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
intel_dpll_mgr.c 1590 temp |= pll->state.hw_state.pll9;
1706 hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1707 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1862 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1933 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
1942 hw_state->pll9,
intel_display.c 13685 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);

Completed in 24 milliseconds