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    Searched refs:pll_settings (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_clock_source.c 188 * pll_settings Pointer to structure
201 struct pll_settings *pll_settings,
214 pll_settings->adjusted_pix_clk_100hz,
233 pll_settings->adjusted_pix_clk_100hz)
235 pll_settings->adjusted_pix_clk_100hz
236 : pll_settings->adjusted_pix_clk_100hz -
241 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
242 pll_settings->reference_divider = ref_divider;
243 pll_settings->feedback_divider = feedback_divider
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
clock_source.h 108 struct pll_settings { struct
166 struct pixel_clk_params *, struct pll_settings *);
170 struct pll_settings *);
core_types.h 287 struct pll_settings pll_settings; member in struct:pipe_ctx
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 126 &pipes[i].pll_settings);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 1181 pipe_ctx->pll_settings.feedback_divider;
1191 pipe_ctx->pll_settings.ss_percentage;
1298 &pipe_ctx->pll_settings)) {
amdgpu_dce110_resource.c 901 &pipe_ctx->pll_settings);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c 1072 &pipe_ctx->pll_settings);
amdgpu_dcn10_hw_sequencer.c 803 &pipe_ctx->pll_settings)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 648 &pipe_ctx->pll_settings)) {
amdgpu_dcn20_resource.c 1496 &pipe_ctx->pll_settings);

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