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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dsc.c 35 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
202 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
203 dsc_log_pps(dsc, &dsc20->reg_vals.pps);
217 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
219 DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
222 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
223 dsc_log_pps(dsc, &dsc_reg_vals.pps);
279 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
282 int bits_per_pixel = pps->bits_per_pixel;
284 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
dscc_types.h 44 struct drm_dsc_config pps; member in struct:dsc_parameters
51 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params);
amdgpu_rc_calc_dpi.c 106 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params)
108 enum colour_mode mode = pps->convert_rgb ? CM_RGB :
109 (pps->simple_422 ? CM_444 :
110 (pps->native_422 ? CM_422 :
111 pps->native_420 ? CM_420 : CM_444));
112 enum bits_per_comp bpc = (pps->bits_per_component == 8) ? BPC_8 :
113 (pps->bits_per_component == 10) ? BPC_10 : BPC_12;
114 float bpp = ((float) pps->bits_per_pixel / 16.0);
115 int slice_width = pps->slice_width;
116 int slice_height = pps->slice_height
    [all...]
  /src/sys/external/bsd/drm2/include/drm/
drm_mipi_dsi.h 49 struct drm_dsc_picture_parameter_set *pps)
  /src/sys/kern/
kern_tc.c 954 * PPS events, so instead we poll them. There is a finite risk that
1061 * RFC 2783 PPS-API implementation.
1065 pps_ioctl(u_long cmd, void *data, struct pps_state *pps)
1075 KASSERT(pps != NULL);
1084 if (app->mode & ~pps->ppscap)
1086 pps->ppsparam = *app;
1090 *app = pps->ppsparam;
1094 *(int*)data = pps->ppscap;
1098 pps->ppsinfo.current_mode = pps->ppsparam.mode
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_lvds.c 160 struct intel_lvds_pps *pps)
164 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
167 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
168 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
169 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
172 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
173 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
186 pps->t4 = val * 1000;
189 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0)
    [all...]
intel_dsi_vbt.c 707 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; local in function:intel_dsi_vbt_init
792 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
793 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
794 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
795 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
796 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
intel_bios.c 741 dev_priv->vbt.edp.pps = *edp_pps;
988 const struct mipi_pps_data *pps; local in function:parse_mipi_config
1017 * get hold of the correct configuration block and pps data as per
1021 pps = &start->pps[panel_type];
1028 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
1029 if (!dev_priv->vbt.dsi.pps) {
2153 kfree(dev_priv->vbt.dsi.pps);
2154 dev_priv->vbt.dsi.pps = NULL
    [all...]
  /src/usr.sbin/spray/
spray.c 201 double pps; /* packets per second */ local in function:print_xferstats
205 pps = packets / xfertime;
208 printf("\t%.0f packets/sec, ", pps);
  /src/usr.sbin/altq/altqstat/
altqstat.c 218 double pps; local in function:calc_pps
220 pps = (double)(new_pkts - last_pkts) / interval;
221 return (pps);
  /src/sys/external/bsd/vchiq/dist/interface/compat/
vchi_bsd.c 222 rlprintf(int pps, const char *fmt, ...)
228 if (ppsratecheck(&last_printf, &count, pps)) {
236 device_rlprintf(int pps, device_t dev, const char *fmt, ...)
242 if (ppsratecheck(&last_printf, &count, pps)) {
vchi_bsd.h 170 void rlprintf(int pps, const char *fmt, ...)
174 device_rlprintf(int pps, device_t dev, const char *fmt, ...)
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
omap3-gta04a5.dts 29 pps {
30 compatible = "pps-gpio";
  /src/sys/uvm/
uvm_pager.c 183 uvm_pagermapin(struct vm_page **pps, int npages, int flags)
191 const u_int first_color = VM_PGCOLOR(*pps);
193 UVMHIST_CALLARGS(maphist,"(pps=%#jx, npages=%jd, first_color=%ju)",
194 (uintptr_t)pps, npages, first_color, 0);
203 KASSERT((pps[0]->flags & PG_BUSY) != 0);
204 error = pmap_direct_process(VM_PAGE_TO_PHYS(pps[0]), 0,
258 pp = *pps++;
uvm_aobj.c 800 * => NOTE: offset is the offset of pps[0], _NOT_ pps[centeridx]
805 uao_get(struct uvm_object *uobj, voff_t offset, struct vm_page **pps,
875 pps[lcv] = ptmp;
886 (pps[centeridx] != NULL), 0,0,0);
888 return pps[centeridx] != NULL ? 0 : EBUSY;
904 * we have yet to locate the current page (pps[lcv]). we
910 * busy it (so we own it) and plug it into pps[lcv]. we are
944 pps[lcv++] = ptmp;
1023 uvm_page_unbusy(pps, lcv)
    [all...]
uvm_device.c 373 * => NOTE: vaddr is the VA of pps[0] in ufi->entry, _NOT_ pps[centeridx]
377 udv_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, struct vm_page **pps,
426 /* pmap va = vaddr (virtual address of pps[0]) */
439 if (pps[lcv] == PGO_DONTCARE)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-venice-gw71xx.dtsi 36 pps {
37 compatible = "pps-gpio";
imx8mm-venice-gw72xx.dtsi 36 pps {
37 compatible = "pps-gpio";
imx8mm-venice-gw73xx.dtsi 36 pps {
37 compatible = "pps-gpio";
  /src/sys/external/bsd/drm2/ttm/
ttm_bo_vm.c 169 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
273 if (pps[i] == PGO_DONTCARE)
312 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
336 ret = ttm_bo_uvm_fault_reserved(vmf, vaddr, pps, npages, centeridx,
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_mman.c 306 vaddr_t vaddr, struct vm_page **pps, int npages, int centeridx, int flags)
374 if (pps[i] == PGO_DONTCARE)
405 vaddr_t vaddr, struct vm_page **pps, int npages, int centeridx, int flags)
513 if (pps[i] == PGO_DONTCARE)
572 i915_gem_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, struct vm_page **pps,
602 error = vm_fault_cpu(ufi, mmo, vaddr, pps, npages, centeridx,
606 error = vm_fault_gtt(ufi, mmo, vaddr, pps, npages, centeridx,
1014 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
  /src/sys/dev/ppbus/
pps_ppbus.c 52 struct pps_state pps_state; /* pps state */
57 CFATTACH_DECL_NEW(pps, sizeof(struct pps_softc), pps_probe, pps_attach,
  /src/sys/external/bsd/drm2/drm/
drm_gem_cma_helper.c 180 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type,
206 if (pps[lcv] == PGO_DONTCARE)
  /src/sys/arch/aarch64/aarch64/
pmap.c 1789 struct pmap_page *pp, *opp, *pps[2]; local in function:_pmap_enter
1900 pps[0] = pp;
1901 pps[1] = NULL;
1942 pps[0] = pp;
1943 pps[1] = opp;
1945 pps[0] = opp;
1946 pps[1] = pp;
1948 if (pps[0] != NULL)
1949 pmap_pv_lock(pps[0]);
1950 if (pps[1] != NULL
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/
drm_mipi_dsi.c 569 /* Note: Needs updating for non-default PPS or algorithm */
584 * mipi_dsi_picture_parameter_set() - transmit the DSC PPS to the peripheral
586 * @pps: VESA DSC 1.1 Picture Parameter Set
593 const struct drm_dsc_picture_parameter_set *pps)
598 .tx_len = sizeof(*pps),
599 .tx_buf = pps,

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