| /src/sys/arch/aarch64/include/ |
| locore.h | 58 #define cpsie(psw) daif_enable((psw))
59 #define cpsid(psw) daif_disable((psw))
71 daif_enable(register_t psw)
73 if (!__builtin_constant_p(psw)) {
74 reg_daif_write(reg_daif_read() & ~psw);
76 reg_daifclr_write((psw & DAIF_MASK) >> DAIF_SETCLR_SHIFT);
81 daif_disable(register_t psw)
84 if ((oldpsw & psw) != psw)
[all...] |
| /src/sys/arch/arm/xscale/ |
| pxa2x0_intr.h | 79 int psw; local
81 psw = disable_interrupts(I32_bit);
83 restore_interrupts(psw);
94 int old, psw; local
98 psw = disable_interrupts(I32_bit);
100 restore_interrupts(psw);
110 int psw = disable_interrupts(I32_bit); local
113 restore_interrupts(psw);
|
| pxa2x0_intr.c | 228 int psw = disable_interrupts(I32_bit); local
247 restore_interrupts(psw);
287 int psw; local
293 psw = disable_interrupts(I32_bit);
302 restore_interrupts(psw);
313 int psw; local
318 psw = disable_interrupts(I32_bit);
326 restore_interrupts(psw);
|
| /src/sys/arch/arm/cortex/ |
| gic_splfuncs.c | 58 register_t psw = DISABLE_INTERRUPT_SAVE(); local
60 pic_do_pending_ints(psw, newipl, NULL);
62 if ((psw & I32_bit) == 0 || newipl == IPL_NONE) {
75 register_t psw; local
81 psw = DISABLE_INTERRUPT_SAVE();
83 pic_do_pending_ints(psw, newipl, NULL);
85 if ((psw & I32_bit) == 0) {
|
| /src/sys/arch/arm/s3c2xx0/ |
| s3c2xx0_intr.h | 131 int psw; local
133 psw = disable_interrupts(I32_bit);
135 restore_interrupts(psw);
146 int old, psw; local
150 psw = disable_interrupts(I32_bit);
152 restore_interrupts(psw);
162 int psw = disable_interrupts(I32_bit); local
164 restore_interrupts(psw);
|
| /src/sys/arch/arm/pic/ |
| pic_splfuncs.c | 71 register_t psw = DISABLE_INTERRUPT_SAVE(); local
73 pic_do_pending_ints(psw, newipl, NULL);
75 if ((psw & I32_bit) == 0 || newipl == IPL_NONE)
93 register_t psw = DISABLE_INTERRUPT_SAVE(); local
98 pic_do_pending_ints(psw, savedipl, NULL);
102 if ((psw & I32_bit) == 0)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/sw/ |
| nouveau_nvkm_engine_sw_nv10.c | 70 nv10_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw)
72 return nvkm_sw_new_(&nv10_sw, device, index, psw);
|
| nouveau_nvkm_engine_sw_nv04.c | 141 nv04_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw)
143 return nvkm_sw_new_(&nv04_sw, device, index, psw);
|
| nouveau_nvkm_engine_sw_base.c | 105 int index, struct nvkm_sw **psw)
109 if (!(sw = *psw = kzalloc(sizeof(*sw), GFP_KERNEL)))
|
| /src/sys/arch/evbarm/lubbock/ |
| obio.c | 95 int psw; local
99 psw = disable_interrupts(I32_bit|F32_bit);
106 restore_interrupts(psw);
141 psw = disable_interrupts(I32_bit|F32_bit);
146 restore_interrupts(psw);
163 int psw; local
166 psw = disable_interrupts(I32_bit);
170 restore_interrupts(psw);
177 psw = disable_interrupts(I32_bit);
183 restore_interrupts(psw);
312 int psw; local
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/ |
| m32r-linux-nat.c | 82 unsigned long psw, bbpsw;
84 psw = *(regp + PSW_REGMAP);
94 regval = ((0x00c1 & bbpsw) << 8) | ((0xc100 & psw) >> 8);
97 regval = ((psw >> 8) & 1);
106 else if (psw & 0x8000)
137 unsigned long psw, bbpsw, tmp;
139 psw = *(regp + PSW_REGMAP);
155 else if (psw & 0x8000)
80 unsigned long psw, bbpsw; local
135 unsigned long psw, bbpsw, tmp; local
|
| m32r-linux-tdep.c | 210 16 * 4, /* psw */
335 4 * 19, /* psw */
360 ULONGEST psw, bbpsw;
365 psw = extract_unsigned_integer (regs + PSW_OFFSET, 4, byte_order);
367 psw = ((0x00c1 & bbpsw) << 8) | ((0xc100 & psw) >> 8);
377 store_unsigned_integer (buf, 4, byte_order, psw);
381 store_unsigned_integer (buf, 4, byte_order, psw & 1);
385 p = regs + ((psw & 0x80) ? SPU_OFFSET : SPI_OFFSET);
404 ULONGEST psw;
359 ULONGEST psw, bbpsw; local
403 ULONGEST psw; local
[all...] |
| /src/external/gpl3/gdb/dist/gdb/ |
| m32r-linux-nat.c | 82 unsigned long psw, bbpsw;
84 psw = *(regp + PSW_REGMAP);
94 regval = ((0x00c1 & bbpsw) << 8) | ((0xc100 & psw) >> 8);
97 regval = ((psw >> 8) & 1);
106 else if (psw & 0x8000)
137 unsigned long psw, bbpsw, tmp;
139 psw = *(regp + PSW_REGMAP);
155 else if (psw & 0x8000)
80 unsigned long psw, bbpsw; local
135 unsigned long psw, bbpsw, tmp; local
|
| m32r-linux-tdep.c | 211 16 * 4, /* psw */
337 4 * 19, /* psw */
362 ULONGEST psw, bbpsw;
367 psw = extract_unsigned_integer (regs + PSW_OFFSET, 4, byte_order);
369 psw = ((0x00c1 & bbpsw) << 8) | ((0xc100 & psw) >> 8);
379 store_unsigned_integer (buf, 4, byte_order, psw);
383 store_unsigned_integer (buf, 4, byte_order, psw & 1);
387 p = regs + ((psw & 0x80) ? SPU_OFFSET : SPI_OFFSET);
406 ULONGEST psw;
361 ULONGEST psw, bbpsw; local
405 ULONGEST psw; local
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/v850/ |
| testutils.inc | 186 stsr psw, r10
194 stsr psw, r10
196 ldsr r10, psw
200 stsr psw, r10
202 ldsr r10, psw
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/v850/ |
| testutils.inc | 186 stsr psw, r10
194 stsr psw, r10
196 ldsr r10, psw
200 stsr psw, r10
202 ldsr r10, psw
|
| /src/external/gpl3/gdb/dist/sim/testsuite/d10v/ |
| t-mvtc.s | 10 ;;; Try out each bit in the PSW
73 ;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero
77 mvtc r6, psw
78 mvfc r7, psw
97 mvtc r6, psw
98 mvfc r7, psw
117 mvtc r6, psw
118 mvfc r7, psw
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/d10v/ |
| t-mvtc.s | 10 ;;; Try out each bit in the PSW
73 ;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero
77 mvtc r6, psw
78 mvfc r7, psw
97 mvtc r6, psw
98 mvfc r7, psw
117 mvtc r6, psw
118 mvfc r7, psw
|
| /src/sys/arch/arm/include/ |
| cpufunc.h | 370 static inline void cpsie(register_t psw) __attribute__((__unused__));
371 static inline register_t cpsid(register_t psw) __attribute__((__unused__));
374 cpsie(register_t psw)
377 if (!__builtin_constant_p(psw)) {
378 enable_interrupts(psw);
381 switch (psw & (I32_bit|F32_bit)) {
387 enable_interrupts(psw);
392 cpsid(register_t psw)
396 if (!__builtin_constant_p(psw))
397 return disable_interrupts(psw);
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/rl78/ |
| cpu.c | 58 /* This maps PSW to a pointer into memory[] */
187 int psw = get_reg (RL78_Reg_PSW); local
188 int z = (psw & RL78_PSW_Z) ? 1 : 0;
189 int cy = (psw & RL78_PSW_CY) ? 1 : 0;
230 "psw",
238 psw_string (int psw)
244 if (psw == 0)
248 #define PSW1(bit, name) if (psw & bit) { strcat (buf, comma); strcat (buf, name); comma = ","; }
321 printf ("PSW: \033[31m");
|
| /src/external/gpl3/gdb/dist/sim/rl78/ |
| cpu.c | 58 /* This maps PSW to a pointer into memory[] */
187 int psw = get_reg (RL78_Reg_PSW); local
188 int z = (psw & RL78_PSW_Z) ? 1 : 0;
189 int cy = (psw & RL78_PSW_CY) ? 1 : 0;
230 "psw",
238 psw_string (int psw)
244 if (psw == 0)
248 #define PSW1(bit, name) if (psw & bit) { strcat (buf, comma); strcat (buf, name); comma = ","; }
321 printf ("PSW: \033[31m");
|
| /src/sys/arch/evbarm/g42xxeb/ |
| obio.c | 119 int psw = disable_interrupts(I32_bit); /* XXX */ local
126 restore_interrupts(psw);
156 int psw; local
158 psw = disable_interrupts(I32_bit);
162 restore_interrupts(psw);
169 psw = disable_interrupts(I32_bit);
178 restore_interrupts(psw);
|
| /src/sys/dev/acpi/ |
| thinkpad_acpi.c | 255 struct sysmon_pswitch *psw; local
363 psw = sc->sc_smpsw;
366 psw[TP_PSW_SLEEP].smpsw_name = device_xname(self);
367 psw[TP_PSW_SLEEP].smpsw_type = PSWITCH_TYPE_SLEEP;
369 psw[TP_PSW_HIBERNATE].smpsw_name = device_xname(self);
375 psw[TP_PSW_DISPLAY_CYCLE].smpsw_name = PSWITCH_HK_DISPLAY_CYCLE;
376 psw[TP_PSW_LOCK_SCREEN].smpsw_name = PSWITCH_HK_LOCK_SCREEN;
377 psw[TP_PSW_BATTERY_INFO].smpsw_name = PSWITCH_HK_BATTERY_INFO;
378 psw[TP_PSW_EJECT_BUTTON].smpsw_name = PSWITCH_HK_EJECT_BUTTON;
379 psw[TP_PSW_ZOOM_BUTTON].smpsw_name = PSWITCH_HK_ZOOM_BUTTON
[all...] |
| /src/sys/arch/arm/gemini/ |
| gemini_ipm.c | 167 int psw; local
177 psw = disable_interrupts(I32_bit);
195 restore_interrupts(psw);
205 int psw; local
210 psw = disable_interrupts(I32_bit);
215 restore_interrupts(psw);
|
| gemini_timer.c | 157 int psw; local
159 psw = disable_interrupts(I32_bit);
163 restore_interrupts(psw);
260 int psw; local
262 psw = disable_interrupts(I32_bit);
270 restore_interrupts(psw);
|
