1 /* $NetBSD: dwc2_core.c,v 1.15 2026/08/17 16:11:28 skrll Exp $ */ 2 3 /* 4 * core.c - DesignWare HS OTG Controller common routines 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * The Core code provides basic services for accessing and managing the 41 * DWC_otg hardware. These services are used by both the Host Controller 42 * Driver and the Peripheral Controller Driver. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.15 2026/08/17 16:11:28 skrll Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/bus.h> 50 #include <sys/proc.h> 51 #include <sys/callout.h> 52 #include <sys/mutex.h> 53 #include <sys/pool.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usb_mem.h> 59 60 #include <linux/kernel.h> 61 #include <linux/list.h> 62 63 #include <dwc2/dwc2.h> 64 #include <dwc2/dwc2var.h> 65 66 #include "dwc2_core.h" 67 #include "dwc2_hcd.h" 68 69 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 70 /** 71 * dwc2_backup_host_registers() - Backup controller host registers. 72 * When suspending usb bus, registers needs to be backuped 73 * if controller power is disabled once suspended. 74 * 75 * @hsotg: Programming view of the DWC_otg controller 76 */ 77 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 78 { 79 struct dwc2_hregs_backup *hr; 80 int i; 81 82 dev_dbg(hsotg->dev, "%s\n", __func__); 83 84 /* Backup Host regs */ 85 hr = &hsotg->hr_backup; 86 hr->hcfg = DWC2_READ_4(hsotg, HCFG); 87 hr->haintmsk = DWC2_READ_4(hsotg, HAINTMSK); 88 for (i = 0; i < hsotg->core_params->host_channels; ++i) 89 hr->hcintmsk[i] = DWC2_READ_4(hsotg, HCINTMSK(i)); 90 91 hr->hprt0 = DWC2_READ_4(hsotg, HPRT0); 92 hr->hfir = DWC2_READ_4(hsotg, HFIR); 93 hr->valid = true; 94 95 return 0; 96 } 97 98 /** 99 * dwc2_restore_host_registers() - Restore controller host registers. 100 * When resuming usb bus, device registers needs to be restored 101 * if controller power were disabled. 102 * 103 * @hsotg: Programming view of the DWC_otg controller 104 */ 105 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 106 { 107 struct dwc2_hregs_backup *hr; 108 int i; 109 110 dev_dbg(hsotg->dev, "%s\n", __func__); 111 112 /* Restore host regs */ 113 hr = &hsotg->hr_backup; 114 if (!hr->valid) { 115 dev_err(hsotg->dev, "%s: no host registers to restore\n", 116 __func__); 117 return -EINVAL; 118 } 119 hr->valid = false; 120 121 DWC2_WRITE_4(hsotg, HCFG, hr->hcfg); 122 DWC2_WRITE_4(hsotg, HAINTMSK, hr->haintmsk); 123 124 for (i = 0; i < hsotg->core_params->host_channels; ++i) 125 DWC2_WRITE_4(hsotg, HCINTMSK(i), hr->hcintmsk[i]); 126 127 DWC2_WRITE_4(hsotg, HPRT0, hr->hprt0); 128 DWC2_WRITE_4(hsotg, HFIR, hr->hfir); 129 hsotg->frame_number = 0; 130 131 return 0; 132 } 133 #else 134 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 135 { return 0; } 136 137 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 138 { return 0; } 139 #endif 140 141 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 142 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 143 /** 144 * dwc2_backup_device_registers() - Backup controller device registers. 145 * When suspending usb bus, registers needs to be backuped 146 * if controller power is disabled once suspended. 147 * 148 * @hsotg: Programming view of the DWC_otg controller 149 */ 150 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 151 { 152 struct dwc2_dregs_backup *dr; 153 int i; 154 155 dev_dbg(hsotg->dev, "%s\n", __func__); 156 157 /* Backup dev regs */ 158 dr = &hsotg->dr_backup; 159 160 dr->dcfg = DWC2_READ_4(hsotg, DCFG); 161 dr->dctl = DWC2_READ_4(hsotg, DCTL); 162 dr->daintmsk = DWC2_READ_4(hsotg, DAINTMSK); 163 dr->diepmsk = DWC2_READ_4(hsotg, DIEPMSK); 164 dr->doepmsk = DWC2_READ_4(hsotg, DOEPMSK); 165 166 for (i = 0; i < hsotg->num_of_eps; i++) { 167 /* Backup IN EPs */ 168 dr->diepctl[i] = DWC2_READ_4(hsotg, DIEPCTL(i)); 169 170 /* Ensure DATA PID is correctly configured */ 171 if (dr->diepctl[i] & DXEPCTL_DPID) 172 dr->diepctl[i] |= DXEPCTL_SETD1PID; 173 else 174 dr->diepctl[i] |= DXEPCTL_SETD0PID; 175 176 dr->dieptsiz[i] = DWC2_READ_4(hsotg, DIEPTSIZ(i)); 177 dr->diepdma[i] = DWC2_READ_4(hsotg, DIEPDMA(i)); 178 179 /* Backup OUT EPs */ 180 dr->doepctl[i] = DWC2_READ_4(hsotg, DOEPCTL(i)); 181 182 /* Ensure DATA PID is correctly configured */ 183 if (dr->doepctl[i] & DXEPCTL_DPID) 184 dr->doepctl[i] |= DXEPCTL_SETD1PID; 185 else 186 dr->doepctl[i] |= DXEPCTL_SETD0PID; 187 188 dr->doeptsiz[i] = DWC2_READ_4(hsotg, DOEPTSIZ(i)); 189 dr->doepdma[i] = DWC2_READ_4(hsotg, DOEPDMA(i)); 190 } 191 dr->valid = true; 192 return 0; 193 } 194 195 /** 196 * dwc2_restore_device_registers() - Restore controller device registers. 197 * When resuming usb bus, device registers needs to be restored 198 * if controller power were disabled. 199 * 200 * @hsotg: Programming view of the DWC_otg controller 201 */ 202 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 203 { 204 struct dwc2_dregs_backup *dr; 205 u32 dctl; 206 int i; 207 208 dev_dbg(hsotg->dev, "%s\n", __func__); 209 210 /* Restore dev regs */ 211 dr = &hsotg->dr_backup; 212 if (!dr->valid) { 213 dev_err(hsotg->dev, "%s: no device registers to restore\n", 214 __func__); 215 return -EINVAL; 216 } 217 dr->valid = false; 218 219 DWC2_WRITE_4(hsotg, DCFG, dr->dcfg); 220 DWC2_WRITE_4(hsotg, DCTL, dr->dctl); 221 DWC2_WRITE_4(hsotg, DAINTMSK, dr->daintmsk); 222 DWC2_WRITE_4(hsotg, DIEPMSK, dr->diepmsk); 223 DWC2_WRITE_4(hsotg, DOEPMSK, dr->doepmsk); 224 225 for (i = 0; i < hsotg->num_of_eps; i++) { 226 /* Restore IN EPs */ 227 DWC2_WRITE_4(hsotg, DIEPCTL(i), dr->diepctl[i]); 228 DWC2_WRITE_4(hsotg, DIEPTSIZ(i), dr->dieptsiz[i]); 229 DWC2_WRITE_4(hsotg, DIEPDMA(i), dr->diepdma[i]); 230 231 /* Restore OUT EPs */ 232 DWC2_WRITE_4(hsotg, DOEPCTL(i), dr->doepctl[i]); 233 DWC2_WRITE_4(hsotg, DOEPTSIZ(i), dr->doeptsiz[i]); 234 DWC2_WRITE_4(hsotg, DOEPDMA(i), dr->doepdma[i]); 235 } 236 237 /* Set the Power-On Programming done bit */ 238 dctl = DWC2_READ_4(hsotg, DCTL); 239 dctl |= DCTL_PWRONPRGDONE; 240 DWC2_WRITE_4(hsotg, DCTL, dctl); 241 242 return 0; 243 } 244 #else 245 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 246 { return 0; } 247 248 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 249 { return 0; } 250 #endif 251 252 /** 253 * dwc2_backup_global_registers() - Backup global controller registers. 254 * When suspending usb bus, registers needs to be backuped 255 * if controller power is disabled once suspended. 256 * 257 * @hsotg: Programming view of the DWC_otg controller 258 */ 259 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 260 { 261 struct dwc2_gregs_backup *gr; 262 int i; 263 264 /* Backup global regs */ 265 gr = &hsotg->gr_backup; 266 267 gr->gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 268 gr->gintmsk = DWC2_READ_4(hsotg, GINTMSK); 269 gr->gahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 270 gr->gusbcfg = DWC2_READ_4(hsotg, GUSBCFG); 271 gr->grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ); 272 gr->gnptxfsiz = DWC2_READ_4(hsotg, GNPTXFSIZ); 273 gr->hptxfsiz = DWC2_READ_4(hsotg, HPTXFSIZ); 274 gr->gdfifocfg = DWC2_READ_4(hsotg, GDFIFOCFG); 275 for (i = 0; i < MAX_EPS_CHANNELS; i++) 276 gr->dtxfsiz[i] = DWC2_READ_4(hsotg, DPTXFSIZN(i)); 277 278 gr->valid = true; 279 return 0; 280 } 281 282 /** 283 * dwc2_restore_global_registers() - Restore controller global registers. 284 * When resuming usb bus, device registers needs to be restored 285 * if controller power were disabled. 286 * 287 * @hsotg: Programming view of the DWC_otg controller 288 */ 289 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 290 { 291 struct dwc2_gregs_backup *gr; 292 int i; 293 294 dev_dbg(hsotg->dev, "%s\n", __func__); 295 296 /* Restore global regs */ 297 gr = &hsotg->gr_backup; 298 if (!gr->valid) { 299 dev_err(hsotg->dev, "%s: no global registers to restore\n", 300 __func__); 301 return -EINVAL; 302 } 303 gr->valid = false; 304 305 DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff); 306 DWC2_WRITE_4(hsotg, GOTGCTL, gr->gotgctl); 307 DWC2_WRITE_4(hsotg, GINTMSK, gr->gintmsk); 308 DWC2_WRITE_4(hsotg, GUSBCFG, gr->gusbcfg); 309 DWC2_WRITE_4(hsotg, GAHBCFG, gr->gahbcfg); 310 DWC2_WRITE_4(hsotg, GRXFSIZ, gr->grxfsiz); 311 DWC2_WRITE_4(hsotg, GNPTXFSIZ, gr->gnptxfsiz); 312 DWC2_WRITE_4(hsotg, HPTXFSIZ, gr->hptxfsiz); 313 DWC2_WRITE_4(hsotg, GDFIFOCFG, gr->gdfifocfg); 314 for (i = 0; i < MAX_EPS_CHANNELS; i++) 315 DWC2_WRITE_4(hsotg, DPTXFSIZN(i), gr->dtxfsiz[i]); 316 317 return 0; 318 } 319 320 /** 321 * dwc2_exit_hibernation() - Exit controller from Partial Power Down. 322 * 323 * @hsotg: Programming view of the DWC_otg controller 324 * @restore: Controller registers need to be restored 325 */ 326 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) 327 { 328 u32 pcgcctl; 329 int ret = 0; 330 331 if (!hsotg->core_params->hibernation) 332 return -ENOTSUPP; 333 334 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 335 pcgcctl &= ~PCGCTL_STOPPCLK; 336 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 337 338 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 339 pcgcctl &= ~PCGCTL_PWRCLMP; 340 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 341 342 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 343 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 344 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 345 346 udelay(100); 347 if (restore) { 348 ret = dwc2_restore_global_registers(hsotg); 349 if (ret) { 350 dev_err(hsotg->dev, "%s: failed to restore registers\n", 351 __func__); 352 return ret; 353 } 354 if (dwc2_is_host_mode(hsotg)) { 355 ret = dwc2_restore_host_registers(hsotg); 356 if (ret) { 357 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 358 __func__); 359 return ret; 360 } 361 } else { 362 ret = dwc2_restore_device_registers(hsotg); 363 if (ret) { 364 dev_err(hsotg->dev, "%s: failed to restore device registers\n", 365 __func__); 366 return ret; 367 } 368 } 369 } 370 371 return ret; 372 } 373 374 /** 375 * dwc2_enter_hibernation() - Put controller in Partial Power Down. 376 * 377 * @hsotg: Programming view of the DWC_otg controller 378 */ 379 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) 380 { 381 u32 pcgcctl; 382 int ret = 0; 383 384 if (!hsotg->core_params->hibernation) 385 return -ENOTSUPP; 386 387 /* Backup all registers */ 388 ret = dwc2_backup_global_registers(hsotg); 389 if (ret) { 390 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 391 __func__); 392 return ret; 393 } 394 395 if (dwc2_is_host_mode(hsotg)) { 396 ret = dwc2_backup_host_registers(hsotg); 397 if (ret) { 398 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 399 __func__); 400 return ret; 401 } 402 } else { 403 ret = dwc2_backup_device_registers(hsotg); 404 if (ret) { 405 dev_err(hsotg->dev, "%s: failed to backup device registers\n", 406 __func__); 407 return ret; 408 } 409 } 410 411 /* 412 * Clear any pending interrupts since dwc2 will not be able to 413 * clear them after entering hibernation. 414 */ 415 DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff); 416 417 /* Put the controller in low power state */ 418 pcgcctl = DWC2_READ_4(hsotg, PCGCTL); 419 420 pcgcctl |= PCGCTL_PWRCLMP; 421 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 422 ndelay(20); 423 424 pcgcctl |= PCGCTL_RSTPDWNMODULE; 425 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 426 ndelay(20); 427 428 pcgcctl |= PCGCTL_STOPPCLK; 429 DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl); 430 431 return ret; 432 } 433 434 /** 435 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 436 * used in both device and host modes 437 * 438 * @hsotg: Programming view of the DWC_otg controller 439 */ 440 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 441 { 442 u32 intmsk; 443 444 /* Clear any pending OTG Interrupts */ 445 DWC2_WRITE_4(hsotg, GOTGINT, 0xffffffff); 446 447 /* Clear any pending interrupts */ 448 DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff); 449 450 /* Enable the interrupts in the GINTMSK */ 451 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 452 453 if (hsotg->core_params->dma_enable <= 0) 454 intmsk |= GINTSTS_RXFLVL; 455 if (hsotg->core_params->external_id_pin_ctl <= 0) 456 intmsk |= GINTSTS_CONIDSTSCHNG; 457 458 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 459 GINTSTS_SESSREQINT; 460 461 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 462 } 463 464 /* 465 * Initializes the FSLSPClkSel field of the HCFG register depending on the 466 * PHY type 467 */ 468 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 469 { 470 u32 hcfg, val; 471 472 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 473 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 474 hsotg->core_params->ulpi_fs_ls > 0) || 475 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 476 /* Full speed PHY */ 477 val = HCFG_FSLSPCLKSEL_48_MHZ; 478 } else { 479 /* High speed PHY running at full speed or high speed */ 480 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 481 } 482 483 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 484 hcfg = DWC2_READ_4(hsotg, HCFG); 485 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 486 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 487 DWC2_WRITE_4(hsotg, HCFG, hcfg); 488 } 489 490 /** 491 * dwc2_wait_for_mode() - Waits for the controller mode. 492 * @hsotg: Programming view of the DWC_otg controller. 493 * @host_mode: If true, waits for host mode, otherwise device mode. 494 */ 495 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, 496 bool host_mode) 497 { 498 unsigned int timeout = 110; 499 unsigned int elapsed = 0; 500 501 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", 502 host_mode ? "host" : "device"); 503 504 while (1) { 505 if (dwc2_is_host_mode(hsotg) == host_mode) { 506 dev_vdbg(hsotg->dev, "%s mode set\n", 507 host_mode ? "Host" : "Device"); 508 break; 509 } 510 511 if (elapsed >= timeout) { 512 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", 513 __func__, host_mode ? "host" : "device"); 514 break; 515 } 516 517 msleep(1); 518 elapsed++; 519 } 520 } 521 522 523 /* 524 * Do core a soft reset of the core. Be careful with this because it 525 * resets all the internal state machines of the core. 526 */ 527 int dwc2_core_reset(struct dwc2_hsotg *hsotg) 528 { 529 u32 greset; 530 int count = 0; 531 532 dev_vdbg(hsotg->dev, "%s()\n", __func__); 533 534 /* Core Soft Reset */ 535 greset = DWC2_READ_4(hsotg, GRSTCTL); 536 greset |= GRSTCTL_CSFTRST; 537 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 538 do { 539 udelay(1); 540 greset = DWC2_READ_4(hsotg, GRSTCTL); 541 if (++count > 50) { 542 dev_warn(hsotg->dev, 543 "%s() HANG! Soft Reset GRSTCTL=%0x\n", 544 __func__, greset); 545 return -EBUSY; 546 } 547 } while (greset & GRSTCTL_CSFTRST); 548 549 /* Wait for AHB master IDLE state */ 550 count = 0; 551 do { 552 udelay(1); 553 greset = DWC2_READ_4(hsotg, GRSTCTL); 554 if (++count > 50) { 555 dev_warn(hsotg->dev, 556 "%s() HANG! AHB Idle GRSTCTL=%0x\n", 557 __func__, greset); 558 return -EBUSY; 559 } 560 } while (!(greset & GRSTCTL_AHBIDLE)); 561 562 return 0; 563 } 564 565 /* 566 * Force the mode of the controller. 567 * 568 * Forcing the mode is needed for two cases: 569 * 570 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 571 * controller to stay in a particular mode regardless of ID pin 572 * changes. We do this usually after a core reset. 573 * 574 * 2) During probe we want to read reset values of the hw 575 * configuration registers that are only available in either host or 576 * device mode. We may need to force the mode if the current mode does 577 * not allow us to access the register in the mode that we want. 578 * 579 * In either case it only makes sense to force the mode if the 580 * controller hardware is OTG capable. 581 * 582 * Checks are done in this function to determine whether doing a force 583 * would be valid or not. 584 * 585 * If a force is done, it requires a 25ms delay to take effect. 586 * 587 * Returns true if the mode was forced. 588 */ 589 static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 590 { 591 u32 gusbcfg; 592 u32 set; 593 u32 clear; 594 595 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 596 597 /* 598 * Force mode has no effect if the hardware is not OTG. 599 */ 600 if (!dwc2_hw_is_otg(hsotg)) 601 return false; 602 603 /* 604 * If dr_mode is either peripheral or host only, there is no 605 * need to ever force the mode to the opposite mode. 606 */ 607 if (host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { 608 WARN_ON(1); 609 return false; 610 } 611 612 if (!host && hsotg->dr_mode == USB_DR_MODE_HOST) { 613 WARN_ON(1); 614 return false; 615 } 616 617 gusbcfg = DWC2_READ_4(hsotg, GUSBCFG); 618 619 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 620 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 621 622 gusbcfg &= ~clear; 623 gusbcfg |= set; 624 DWC2_WRITE_4(hsotg, GUSBCFG, gusbcfg); 625 626 dwc2_wait_for_mode(hsotg, host); 627 628 return true; 629 } 630 631 /* 632 * Clears the force mode bits. 633 */ 634 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 635 { 636 u32 gusbcfg; 637 638 gusbcfg = DWC2_READ_4(hsotg, GUSBCFG); 639 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 640 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 641 DWC2_WRITE_4(hsotg, GUSBCFG, gusbcfg); 642 643 /* 644 * NOTE: This long sleep is _very_ important, otherwise the core will 645 * not stay in host mode after a connector ID change! 646 */ 647 msleep(25); 648 } 649 650 /* 651 * Sets or clears force mode based on the dr_mode parameter. 652 */ 653 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 654 { 655 switch (hsotg->dr_mode) { 656 case USB_DR_MODE_HOST: 657 dwc2_force_mode(hsotg, true); 658 break; 659 case USB_DR_MODE_PERIPHERAL: 660 dwc2_force_mode(hsotg, false); 661 break; 662 case USB_DR_MODE_OTG: 663 dwc2_clear_force_mode(hsotg); 664 break; 665 default: 666 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 667 __func__, hsotg->dr_mode); 668 break; 669 } 670 } 671 672 /* 673 * Do core a soft reset of the core. Be careful with this because it 674 * resets all the internal state machines of the core. 675 * 676 * Additionally this will apply force mode as per the hsotg->dr_mode 677 * parameter. 678 */ 679 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg) 680 { 681 int retval; 682 683 retval = dwc2_core_reset(hsotg); 684 if (retval) 685 return retval; 686 687 dwc2_force_dr_mode(hsotg); 688 return 0; 689 } 690 691 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 692 { 693 u32 usbcfg, i2cctl; 694 int retval = 0; 695 696 /* 697 * core_init() is now called on every switch so only call the 698 * following for the first time through 699 */ 700 if (select_phy) { 701 dev_dbg(hsotg->dev, "FS PHY selected\n"); 702 703 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 704 if (!(usbcfg & GUSBCFG_PHYSEL)) { 705 usbcfg |= GUSBCFG_PHYSEL; 706 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 707 708 /* Reset after a PHY select */ 709 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 710 711 if (retval) { 712 dev_err(hsotg->dev, 713 "%s: Reset failed, aborting", __func__); 714 return retval; 715 } 716 } 717 } 718 719 /* 720 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 721 * do this on HNP Dev/Host mode switches (done in dev_init and 722 * host_init). 723 */ 724 if (dwc2_is_host_mode(hsotg)) 725 dwc2_init_fs_ls_pclk_sel(hsotg); 726 727 if (hsotg->core_params->i2c_enable > 0) { 728 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 729 730 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 731 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 732 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 733 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 734 735 /* Program GI2CCTL.I2CEn */ 736 i2cctl = DWC2_READ_4(hsotg, GI2CCTL); 737 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 738 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 739 i2cctl &= ~GI2CCTL_I2CEN; 740 DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl); 741 i2cctl |= GI2CCTL_I2CEN; 742 DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl); 743 } 744 745 return retval; 746 } 747 748 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 749 { 750 u32 usbcfg, usbcfg_old; 751 int retval = 0; 752 753 if (!select_phy) 754 return 0; 755 756 usbcfg = usbcfg_old = DWC2_READ_4(hsotg, GUSBCFG); 757 758 /* 759 * HS PHY parameters. These parameters are preserved during soft reset 760 * so only program the first time. Do a soft reset immediately after 761 * setting phyif. 762 */ 763 switch (hsotg->core_params->phy_type) { 764 case DWC2_PHY_TYPE_PARAM_ULPI: 765 /* ULPI interface */ 766 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 767 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 768 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 769 if (hsotg->core_params->phy_ulpi_ddr > 0) 770 usbcfg |= GUSBCFG_DDRSEL; 771 break; 772 case DWC2_PHY_TYPE_PARAM_UTMI: 773 /* UTMI+ interface */ 774 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 775 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 776 if (hsotg->core_params->phy_utmi_width == 16) 777 usbcfg |= GUSBCFG_PHYIF16; 778 break; 779 default: 780 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 781 break; 782 } 783 784 if (usbcfg != usbcfg_old) { 785 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 786 787 /* Reset after setting the PHY parameters */ 788 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 789 if (retval) { 790 dev_err(hsotg->dev, 791 "%s: Reset failed, aborting", __func__); 792 return retval; 793 } 794 } 795 796 return retval; 797 } 798 799 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 800 { 801 u32 usbcfg; 802 int retval = 0; 803 804 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && 805 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 806 /* If FS mode with FS PHY */ 807 retval = dwc2_fs_phy_init(hsotg, select_phy); 808 if (retval) 809 return retval; 810 } else { 811 /* High speed PHY */ 812 retval = dwc2_hs_phy_init(hsotg, select_phy); 813 if (retval) 814 return retval; 815 } 816 817 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 818 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 819 hsotg->core_params->ulpi_fs_ls > 0) { 820 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 821 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 822 usbcfg |= GUSBCFG_ULPI_FS_LS; 823 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 824 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 825 } else { 826 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 827 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 828 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 829 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 830 } 831 832 return retval; 833 } 834 835 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 836 { 837 struct dwc2_softc *sc = hsotg->hsotg_sc; 838 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 839 840 switch (hsotg->hw_params.arch) { 841 case GHWCFG2_EXT_DMA_ARCH: 842 dev_dbg(hsotg->dev, "External DMA Mode\n"); 843 if (!sc->sc_set_dma_addr) { 844 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 845 return -EINVAL; 846 } 847 if (hsotg->core_params->ahbcfg != -1) { 848 ahbcfg &= GAHBCFG_CTRL_MASK; 849 ahbcfg |= hsotg->core_params->ahbcfg & 850 ~GAHBCFG_CTRL_MASK; 851 } 852 break; 853 854 case GHWCFG2_INT_DMA_ARCH: 855 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 856 if (hsotg->core_params->ahbcfg != -1) { 857 ahbcfg &= GAHBCFG_CTRL_MASK; 858 ahbcfg |= hsotg->core_params->ahbcfg & 859 ~GAHBCFG_CTRL_MASK; 860 } 861 break; 862 863 case GHWCFG2_SLAVE_ONLY_ARCH: 864 default: 865 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 866 break; 867 } 868 869 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", 870 hsotg->core_params->dma_enable, 871 hsotg->core_params->dma_desc_enable); 872 873 if (hsotg->core_params->dma_enable > 0) { 874 if (hsotg->core_params->dma_desc_enable > 0) 875 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 876 else 877 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 878 } else { 879 dev_dbg(hsotg->dev, "Using Slave mode\n"); 880 hsotg->core_params->dma_desc_enable = 0; 881 } 882 883 if (hsotg->core_params->dma_enable > 0) 884 ahbcfg |= GAHBCFG_DMA_EN; 885 886 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 887 888 return 0; 889 } 890 891 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 892 { 893 u32 usbcfg; 894 895 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 896 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 897 898 switch (hsotg->hw_params.op_mode) { 899 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 900 if (hsotg->core_params->otg_cap == 901 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 902 usbcfg |= GUSBCFG_HNPCAP; 903 if (hsotg->core_params->otg_cap != 904 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 905 usbcfg |= GUSBCFG_SRPCAP; 906 break; 907 908 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 909 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 910 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 911 if (hsotg->core_params->otg_cap != 912 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 913 usbcfg |= GUSBCFG_SRPCAP; 914 break; 915 916 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 917 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 918 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 919 default: 920 break; 921 } 922 923 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 924 } 925 926 /** 927 * dwc2_core_init() - Initializes the DWC_otg controller registers and 928 * prepares the core for device mode or host mode operation 929 * 930 * @hsotg: Programming view of the DWC_otg controller 931 * @initial_setup: If true then this is the first init for this instance. 932 */ 933 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 934 { 935 u32 usbcfg, otgctl; 936 int retval; 937 938 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 939 940 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 941 942 /* Set ULPI External VBUS bit if needed */ 943 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 944 if (hsotg->core_params->phy_ulpi_ext_vbus == 945 DWC2_PHY_ULPI_EXTERNAL_VBUS) 946 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 947 948 /* Set external TS Dline pulsing bit if needed */ 949 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 950 if (hsotg->core_params->ts_dline > 0) 951 usbcfg |= GUSBCFG_TERMSELDLPULSE; 952 953 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 954 955 /* 956 * Reset the Controller 957 * 958 * We only need to reset the controller if this is a re-init. 959 * For the first init we know for sure that earlier code reset us (it 960 * needed to in order to properly detect various parameters). 961 */ 962 if (!initial_setup) { 963 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 964 if (retval) { 965 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 966 __func__); 967 return retval; 968 } 969 } 970 971 /* 972 * This needs to happen in FS mode before any other programming occurs 973 */ 974 retval = dwc2_phy_init(hsotg, initial_setup); 975 if (retval) 976 return retval; 977 978 /* Program the GAHBCFG Register */ 979 retval = dwc2_gahbcfg_init(hsotg); 980 if (retval) 981 return retval; 982 983 /* Program the GUSBCFG register */ 984 dwc2_gusbcfg_init(hsotg); 985 986 /* Program the GOTGCTL register */ 987 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 988 otgctl &= ~GOTGCTL_OTGVER; 989 if (hsotg->core_params->otg_ver > 0) 990 otgctl |= GOTGCTL_OTGVER; 991 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 992 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); 993 994 /* Clear the SRP success bit for FS-I2c */ 995 hsotg->srp_success = 0; 996 997 /* Enable common interrupts */ 998 dwc2_enable_common_interrupts(hsotg); 999 1000 /* 1001 * Do device or host initialization based on mode during PCD and 1002 * HCD initialization 1003 */ 1004 if (dwc2_is_host_mode(hsotg)) { 1005 dev_dbg(hsotg->dev, "Host Mode\n"); 1006 hsotg->op_state = OTG_STATE_A_HOST; 1007 } else { 1008 dev_dbg(hsotg->dev, "Device Mode\n"); 1009 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1010 } 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 1017 * 1018 * @hsotg: Programming view of DWC_otg controller 1019 */ 1020 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 1021 { 1022 u32 intmsk; 1023 1024 dev_dbg(hsotg->dev, "%s()\n", __func__); 1025 1026 /* Disable all interrupts */ 1027 DWC2_WRITE_4(hsotg, GINTMSK, 0); 1028 DWC2_WRITE_4(hsotg, HAINTMSK, 0); 1029 1030 /* Enable the common interrupts */ 1031 dwc2_enable_common_interrupts(hsotg); 1032 1033 /* Enable host mode interrupts without disturbing common interrupts */ 1034 intmsk = DWC2_READ_4(hsotg, GINTMSK); 1035 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 1036 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 1037 } 1038 1039 /** 1040 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 1041 * 1042 * @hsotg: Programming view of DWC_otg controller 1043 */ 1044 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 1045 { 1046 u32 intmsk = DWC2_READ_4(hsotg, GINTMSK); 1047 1048 /* Disable host mode interrupts without disturbing common interrupts */ 1049 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 1050 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 1051 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 1052 } 1053 1054 /* 1055 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 1056 * For system that have a total fifo depth that is smaller than the default 1057 * RX + TX fifo size. 1058 * 1059 * @hsotg: Programming view of DWC_otg controller 1060 */ 1061 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 1062 { 1063 struct dwc2_core_params *params = hsotg->core_params; 1064 struct dwc2_hw_params *hw = &hsotg->hw_params; 1065 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 1066 1067 total_fifo_size = hw->total_fifo_size; 1068 rxfsiz = params->host_rx_fifo_size; 1069 nptxfsiz = params->host_nperio_tx_fifo_size; 1070 ptxfsiz = params->host_perio_tx_fifo_size; 1071 1072 /* 1073 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 1074 * allocation with support for high bandwidth endpoints. Synopsys 1075 * defines MPS(Max Packet size) for a periodic EP=1024, and for 1076 * non-periodic as 512. 1077 */ 1078 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 1079 /* 1080 * For Buffer DMA mode/Scatter Gather DMA mode 1081 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 1082 * with n = number of host channel. 1083 * 2 * ((1024/4) + 2) = 516 1084 */ 1085 rxfsiz = 516 + hw->host_channels; 1086 1087 /* 1088 * min non-periodic tx fifo depth 1089 * 2 * (largest non-periodic USB packet used / 4) 1090 * 2 * (512/4) = 256 1091 */ 1092 nptxfsiz = 256; 1093 1094 /* 1095 * min periodic tx fifo depth 1096 * (largest packet size*MC)/4 1097 * (1024 * 3)/4 = 768 1098 */ 1099 ptxfsiz = 768; 1100 1101 params->host_rx_fifo_size = rxfsiz; 1102 params->host_nperio_tx_fifo_size = nptxfsiz; 1103 params->host_perio_tx_fifo_size = ptxfsiz; 1104 } 1105 1106 /* 1107 * If the summation of RX, NPTX and PTX fifo sizes is still 1108 * bigger than the total_fifo_size, then we have a problem. 1109 * 1110 * We won't be able to allocate as many endpoints. Right now, 1111 * we're just printing an error message, but ideally this FIFO 1112 * allocation algorithm would be improved in the future. 1113 * 1114 * FIXME improve this FIFO allocation algorithm. 1115 */ 1116 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 1117 dev_err(hsotg->dev, "invalid fifo sizes\n"); 1118 } 1119 1120 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 1121 { 1122 struct dwc2_core_params *params = hsotg->core_params; 1123 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 1124 1125 if (!params->enable_dynamic_fifo) 1126 return; 1127 1128 dwc2_calculate_dynamic_fifo(hsotg); 1129 1130 /* Rx FIFO */ 1131 grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ); 1132 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 1133 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 1134 grxfsiz |= params->host_rx_fifo_size << 1135 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 1136 DWC2_WRITE_4(hsotg, GRXFSIZ, grxfsiz); 1137 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 1138 DWC2_READ_4(hsotg, GRXFSIZ)); 1139 1140 /* Non-periodic Tx FIFO */ 1141 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 1142 DWC2_READ_4(hsotg, GNPTXFSIZ)); 1143 nptxfsiz = params->host_nperio_tx_fifo_size << 1144 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 1145 nptxfsiz |= params->host_rx_fifo_size << 1146 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 1147 DWC2_WRITE_4(hsotg, GNPTXFSIZ, nptxfsiz); 1148 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 1149 DWC2_READ_4(hsotg, GNPTXFSIZ)); 1150 1151 /* Periodic Tx FIFO */ 1152 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 1153 DWC2_READ_4(hsotg, HPTXFSIZ)); 1154 hptxfsiz = params->host_perio_tx_fifo_size << 1155 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 1156 hptxfsiz |= (params->host_rx_fifo_size + 1157 params->host_nperio_tx_fifo_size) << 1158 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 1159 DWC2_WRITE_4(hsotg, HPTXFSIZ, hptxfsiz); 1160 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 1161 DWC2_READ_4(hsotg, HPTXFSIZ)); 1162 1163 if (hsotg->core_params->en_multiple_tx_fifo > 0 && 1164 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 1165 /* 1166 * Global DFIFOCFG calculation for Host mode - 1167 * include RxFIFO, NPTXFIFO and HPTXFIFO 1168 */ 1169 dfifocfg = DWC2_READ_4(hsotg, GDFIFOCFG); 1170 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 1171 dfifocfg |= (params->host_rx_fifo_size + 1172 params->host_nperio_tx_fifo_size + 1173 params->host_perio_tx_fifo_size) << 1174 GDFIFOCFG_EPINFOBASE_SHIFT & 1175 GDFIFOCFG_EPINFOBASE_MASK; 1176 DWC2_WRITE_4(hsotg, GDFIFOCFG, dfifocfg); 1177 } 1178 } 1179 1180 /** 1181 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 1182 * Host mode 1183 * 1184 * @hsotg: Programming view of DWC_otg controller 1185 * 1186 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 1187 * request queues. Host channels are reset to ensure that they are ready for 1188 * performing transfers. 1189 */ 1190 void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 1191 { 1192 u32 hcfg, hfir, otgctl; 1193 1194 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 1195 1196 /* Restart the Phy Clock */ 1197 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1198 1199 /* Initialize Host Configuration Register */ 1200 dwc2_init_fs_ls_pclk_sel(hsotg); 1201 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { 1202 hcfg = DWC2_READ_4(hsotg, HCFG); 1203 hcfg |= HCFG_FSLSSUPP; 1204 DWC2_WRITE_4(hsotg, HCFG, hcfg); 1205 } 1206 1207 /* 1208 * This bit allows dynamic reloading of the HFIR register during 1209 * runtime. This bit needs to be programmed during initial configuration 1210 * and its value must not be changed during runtime. 1211 */ 1212 if (hsotg->core_params->reload_ctl > 0) { 1213 hfir = DWC2_READ_4(hsotg, HFIR); 1214 hfir |= HFIR_RLDCTRL; 1215 DWC2_WRITE_4(hsotg, HFIR, hfir); 1216 } 1217 1218 if (hsotg->core_params->dma_desc_enable > 0) { 1219 u32 op_mode = hsotg->hw_params.op_mode; 1220 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 1221 !hsotg->hw_params.dma_desc_enable || 1222 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 1223 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 1224 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 1225 dev_err(hsotg->dev, 1226 "Hardware does not support descriptor DMA mode -\n"); 1227 dev_err(hsotg->dev, 1228 "falling back to buffer DMA mode.\n"); 1229 hsotg->core_params->dma_desc_enable = 0; 1230 } else { 1231 hcfg = DWC2_READ_4(hsotg, HCFG); 1232 hcfg |= HCFG_DESCDMA; 1233 DWC2_WRITE_4(hsotg, HCFG, hcfg); 1234 } 1235 } 1236 1237 /* Configure data FIFO sizes */ 1238 dwc2_config_fifos(hsotg); 1239 1240 /* TODO - check this */ 1241 /* Clear Host Set HNP Enable in the OTG Control Register */ 1242 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 1243 otgctl &= ~GOTGCTL_HSTSETHNPEN; 1244 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 1245 1246 /* Make sure the FIFOs are flushed */ 1247 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 1248 dwc2_flush_rx_fifo(hsotg); 1249 1250 /* Clear Host Set HNP Enable in the OTG Control Register */ 1251 otgctl = DWC2_READ_4(hsotg, GOTGCTL); 1252 otgctl &= ~GOTGCTL_HSTSETHNPEN; 1253 DWC2_WRITE_4(hsotg, GOTGCTL, otgctl); 1254 1255 if (hsotg->core_params->dma_desc_enable <= 0) { 1256 int num_channels, i; 1257 u32 hcchar; 1258 1259 /* Flush out any leftover queued requests */ 1260 num_channels = hsotg->core_params->host_channels; 1261 for (i = 0; i < num_channels; i++) { 1262 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 1263 hcchar &= ~HCCHAR_CHENA; 1264 hcchar |= HCCHAR_CHDIS; 1265 hcchar &= ~HCCHAR_EPDIR; 1266 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 1267 } 1268 1269 /* Halt all channels to put them into a known state */ 1270 for (i = 0; i < num_channels; i++) { 1271 int count = 0; 1272 1273 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 1274 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 1275 hcchar &= ~HCCHAR_EPDIR; 1276 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 1277 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 1278 __func__, i); 1279 do { 1280 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 1281 if (++count > 1000) { 1282 dev_err(hsotg->dev, 1283 "Unable to clear enable on channel %d\n", 1284 i); 1285 break; 1286 } 1287 udelay(1); 1288 } while (hcchar & HCCHAR_CHENA); 1289 } 1290 } 1291 1292 /* Turn on the vbus power */ 1293 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 1294 if (hsotg->op_state == OTG_STATE_A_HOST) { 1295 u32 hprt0 = dwc2_read_hprt0(hsotg); 1296 1297 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 1298 !!(hprt0 & HPRT0_PWR)); 1299 if (!(hprt0 & HPRT0_PWR)) { 1300 hprt0 |= HPRT0_PWR; 1301 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1302 } 1303 } 1304 1305 dwc2_enable_host_interrupts(hsotg); 1306 } 1307 1308 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 1309 struct dwc2_host_chan *chan) 1310 { 1311 u32 hcintmsk = HCINTMSK_CHHLTD; 1312 1313 switch (chan->ep_type) { 1314 case USB_ENDPOINT_XFER_CONTROL: 1315 case USB_ENDPOINT_XFER_BULK: 1316 dev_vdbg(hsotg->dev, "control/bulk\n"); 1317 hcintmsk |= HCINTMSK_XFERCOMPL; 1318 hcintmsk |= HCINTMSK_STALL; 1319 hcintmsk |= HCINTMSK_XACTERR; 1320 hcintmsk |= HCINTMSK_DATATGLERR; 1321 if (chan->ep_is_in) { 1322 hcintmsk |= HCINTMSK_BBLERR; 1323 } else { 1324 hcintmsk |= HCINTMSK_NAK; 1325 hcintmsk |= HCINTMSK_NYET; 1326 if (chan->do_ping) 1327 hcintmsk |= HCINTMSK_ACK; 1328 } 1329 1330 if (chan->do_split) { 1331 hcintmsk |= HCINTMSK_NAK; 1332 if (chan->complete_split) 1333 hcintmsk |= HCINTMSK_NYET; 1334 else 1335 hcintmsk |= HCINTMSK_ACK; 1336 } 1337 1338 if (chan->error_state) 1339 hcintmsk |= HCINTMSK_ACK; 1340 break; 1341 1342 case USB_ENDPOINT_XFER_INT: 1343 if (dbg_perio()) 1344 dev_vdbg(hsotg->dev, "intr\n"); 1345 hcintmsk |= HCINTMSK_XFERCOMPL; 1346 hcintmsk |= HCINTMSK_NAK; 1347 hcintmsk |= HCINTMSK_STALL; 1348 hcintmsk |= HCINTMSK_XACTERR; 1349 hcintmsk |= HCINTMSK_DATATGLERR; 1350 hcintmsk |= HCINTMSK_FRMOVRUN; 1351 1352 if (chan->ep_is_in) 1353 hcintmsk |= HCINTMSK_BBLERR; 1354 if (chan->error_state) 1355 hcintmsk |= HCINTMSK_ACK; 1356 if (chan->do_split) { 1357 if (chan->complete_split) 1358 hcintmsk |= HCINTMSK_NYET; 1359 else 1360 hcintmsk |= HCINTMSK_ACK; 1361 } 1362 break; 1363 1364 case USB_ENDPOINT_XFER_ISOC: 1365 if (dbg_perio()) 1366 dev_vdbg(hsotg->dev, "isoc\n"); 1367 hcintmsk |= HCINTMSK_XFERCOMPL; 1368 hcintmsk |= HCINTMSK_FRMOVRUN; 1369 hcintmsk |= HCINTMSK_ACK; 1370 1371 if (chan->ep_is_in) { 1372 hcintmsk |= HCINTMSK_XACTERR; 1373 hcintmsk |= HCINTMSK_BBLERR; 1374 } 1375 break; 1376 default: 1377 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 1378 break; 1379 } 1380 1381 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 1382 if (dbg_hc(chan)) 1383 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 1384 } 1385 1386 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 1387 struct dwc2_host_chan *chan) 1388 { 1389 u32 hcintmsk = HCINTMSK_CHHLTD; 1390 1391 /* 1392 * For Descriptor DMA mode core halts the channel on AHB error. 1393 * Interrupt is not required. 1394 */ 1395 if (hsotg->core_params->dma_desc_enable <= 0) { 1396 if (dbg_hc(chan)) 1397 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1398 hcintmsk |= HCINTMSK_AHBERR; 1399 } else { 1400 if (dbg_hc(chan)) 1401 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 1402 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1403 hcintmsk |= HCINTMSK_XFERCOMPL; 1404 } 1405 1406 if (chan->error_state && !chan->do_split && 1407 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 1408 if (dbg_hc(chan)) 1409 dev_vdbg(hsotg->dev, "setting ACK\n"); 1410 hcintmsk |= HCINTMSK_ACK; 1411 if (chan->ep_is_in) { 1412 hcintmsk |= HCINTMSK_DATATGLERR; 1413 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 1414 hcintmsk |= HCINTMSK_NAK; 1415 } 1416 } 1417 1418 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 1419 if (dbg_hc(chan)) 1420 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 1421 } 1422 1423 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 1424 struct dwc2_host_chan *chan) 1425 { 1426 u32 intmsk; 1427 1428 if (hsotg->core_params->dma_enable > 0) { 1429 if (dbg_hc(chan)) 1430 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1431 dwc2_hc_enable_dma_ints(hsotg, chan); 1432 } else { 1433 if (dbg_hc(chan)) 1434 dev_vdbg(hsotg->dev, "DMA disabled\n"); 1435 dwc2_hc_enable_slave_ints(hsotg, chan); 1436 } 1437 1438 /* Enable the top level host channel interrupt */ 1439 intmsk = DWC2_READ_4(hsotg, HAINTMSK); 1440 intmsk |= 1 << chan->hc_num; 1441 DWC2_WRITE_4(hsotg, HAINTMSK, intmsk); 1442 if (dbg_hc(chan)) 1443 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 1444 1445 /* Make sure host channel interrupts are enabled */ 1446 intmsk = DWC2_READ_4(hsotg, GINTMSK); 1447 intmsk |= GINTSTS_HCHINT; 1448 DWC2_WRITE_4(hsotg, GINTMSK, intmsk); 1449 if (dbg_hc(chan)) 1450 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 1451 } 1452 1453 /** 1454 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 1455 * a specific endpoint 1456 * 1457 * @hsotg: Programming view of DWC_otg controller 1458 * @chan: Information needed to initialize the host channel 1459 * 1460 * The HCCHARn register is set up with the characteristics specified in chan. 1461 * Host channel interrupts that may need to be serviced while this transfer is 1462 * in progress are enabled. 1463 */ 1464 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1465 { 1466 u8 hc_num = chan->hc_num; 1467 u32 hcintmsk; 1468 u32 hcchar; 1469 u32 hcsplt = 0; 1470 1471 if (dbg_hc(chan)) 1472 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1473 1474 /* Clear old interrupt conditions for this host channel */ 1475 hcintmsk = 0xffffffff; 1476 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1477 DWC2_WRITE_4(hsotg, HCINT(hc_num), hcintmsk); 1478 1479 /* Enable channel interrupts required for this transfer */ 1480 dwc2_hc_enable_ints(hsotg, chan); 1481 1482 /* 1483 * Program the HCCHARn register with the endpoint characteristics for 1484 * the current transfer 1485 */ 1486 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 1487 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 1488 if (chan->ep_is_in) 1489 hcchar |= HCCHAR_EPDIR; 1490 if (chan->speed == USB_SPEED_LOW) 1491 hcchar |= HCCHAR_LSPDDEV; 1492 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 1493 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 1494 DWC2_WRITE_4(hsotg, HCCHAR(hc_num), hcchar); 1495 if (dbg_hc(chan)) { 1496 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 1497 hc_num, hcchar); 1498 1499 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 1500 __func__, hc_num); 1501 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 1502 chan->dev_addr); 1503 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 1504 chan->ep_num); 1505 dev_vdbg(hsotg->dev, " Is In: %d\n", 1506 chan->ep_is_in); 1507 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 1508 chan->speed == USB_SPEED_LOW); 1509 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 1510 chan->ep_type); 1511 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 1512 chan->max_packet); 1513 } 1514 1515 /* Program the HCSPLT register for SPLITs */ 1516 if (chan->do_split) { 1517 if (dbg_hc(chan)) 1518 dev_vdbg(hsotg->dev, 1519 "Programming HC %d with split --> %s\n", 1520 hc_num, 1521 chan->complete_split ? "CSPLIT" : "SSPLIT"); 1522 if (chan->complete_split) 1523 hcsplt |= HCSPLT_COMPSPLT; 1524 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 1525 HCSPLT_XACTPOS_MASK; 1526 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 1527 HCSPLT_HUBADDR_MASK; 1528 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 1529 HCSPLT_PRTADDR_MASK; 1530 if (dbg_hc(chan)) { 1531 dev_vdbg(hsotg->dev, " comp split %d\n", 1532 chan->complete_split); 1533 dev_vdbg(hsotg->dev, " xact pos %d\n", 1534 chan->xact_pos); 1535 dev_vdbg(hsotg->dev, " hub addr %d\n", 1536 chan->hub_addr); 1537 dev_vdbg(hsotg->dev, " hub port %d\n", 1538 chan->hub_port); 1539 dev_vdbg(hsotg->dev, " is_in %d\n", 1540 chan->ep_is_in); 1541 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 1542 chan->max_packet); 1543 dev_vdbg(hsotg->dev, " xferlen %d\n", 1544 chan->xfer_len); 1545 } 1546 } 1547 1548 DWC2_WRITE_4(hsotg, HCSPLT(hc_num), hcsplt); 1549 } 1550 1551 /** 1552 * dwc2_hc_halt() - Attempts to halt a host channel 1553 * 1554 * @hsotg: Controller register interface 1555 * @chan: Host channel to halt 1556 * @halt_status: Reason for halting the channel 1557 * 1558 * This function should only be called in Slave mode or to abort a transfer in 1559 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 1560 * controller halts the channel when the transfer is complete or a condition 1561 * occurs that requires application intervention. 1562 * 1563 * In slave mode, checks for a free request queue entry, then sets the Channel 1564 * Enable and Channel Disable bits of the Host Channel Characteristics 1565 * register of the specified channel to intiate the halt. If there is no free 1566 * request queue entry, sets only the Channel Disable bit of the HCCHARn 1567 * register to flush requests for this channel. In the latter case, sets a 1568 * flag to indicate that the host channel needs to be halted when a request 1569 * queue slot is open. 1570 * 1571 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 1572 * HCCHARn register. The controller ensures there is space in the request 1573 * queue before submitting the halt request. 1574 * 1575 * Some time may elapse before the core flushes any posted requests for this 1576 * host channel and halts. The Channel Halted interrupt handler completes the 1577 * deactivation of the host channel. 1578 */ 1579 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 1580 enum dwc2_halt_status halt_status) 1581 { 1582 u32 nptxsts, hptxsts, hcchar; 1583 1584 if (dbg_hc(chan)) 1585 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1586 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 1587 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 1588 1589 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 1590 halt_status == DWC2_HC_XFER_AHB_ERR) { 1591 /* 1592 * Disable all channel interrupts except Ch Halted. The QTD 1593 * and QH state associated with this transfer has been cleared 1594 * (in the case of URB_DEQUEUE), so the channel needs to be 1595 * shut down carefully to prevent crashes. 1596 */ 1597 u32 hcintmsk = HCINTMSK_CHHLTD; 1598 1599 dev_vdbg(hsotg->dev, "dequeue/error\n"); 1600 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), hcintmsk); 1601 1602 /* 1603 * Make sure no other interrupts besides halt are currently 1604 * pending. Handling another interrupt could cause a crash due 1605 * to the QTD and QH state. 1606 */ 1607 DWC2_WRITE_4(hsotg, HCINT(chan->hc_num), ~hcintmsk); 1608 1609 /* 1610 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1611 * even if the channel was already halted for some other 1612 * reason 1613 */ 1614 chan->halt_status = halt_status; 1615 1616 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1617 if (!(hcchar & HCCHAR_CHENA)) { 1618 /* 1619 * The channel is either already halted or it hasn't 1620 * started yet. In DMA mode, the transfer may halt if 1621 * it finishes normally or a condition occurs that 1622 * requires driver intervention. Don't want to halt 1623 * the channel again. In either Slave or DMA mode, 1624 * it's possible that the transfer has been assigned 1625 * to a channel, but not started yet when an URB is 1626 * dequeued. Don't want to halt a channel that hasn't 1627 * started yet. 1628 */ 1629 return; 1630 } 1631 } 1632 if (chan->halt_pending) { 1633 /* 1634 * A halt has already been issued for this channel. This might 1635 * happen when a transfer is aborted by a higher level in 1636 * the stack. 1637 */ 1638 dev_vdbg(hsotg->dev, 1639 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1640 __func__, chan->hc_num); 1641 return; 1642 } 1643 1644 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 1645 1646 /* No need to set the bit in DDMA for disabling the channel */ 1647 /* TODO check it everywhere channel is disabled */ 1648 if (hsotg->core_params->dma_desc_enable <= 0) { 1649 if (dbg_hc(chan)) 1650 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1651 hcchar |= HCCHAR_CHENA; 1652 } else { 1653 if (dbg_hc(chan)) 1654 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1655 } 1656 hcchar |= HCCHAR_CHDIS; 1657 1658 if (hsotg->core_params->dma_enable <= 0) { 1659 if (dbg_hc(chan)) 1660 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1661 hcchar |= HCCHAR_CHENA; 1662 1663 /* Check for space in the request queue to issue the halt */ 1664 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1665 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1666 dev_vdbg(hsotg->dev, "control/bulk\n"); 1667 nptxsts = DWC2_READ_4(hsotg, GNPTXSTS); 1668 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1669 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1670 hcchar &= ~HCCHAR_CHENA; 1671 } 1672 } else { 1673 if (dbg_perio()) 1674 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1675 hptxsts = DWC2_READ_4(hsotg, HPTXSTS); 1676 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1677 hsotg->queuing_high_bandwidth) { 1678 if (dbg_perio()) 1679 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1680 hcchar &= ~HCCHAR_CHENA; 1681 } 1682 } 1683 } else { 1684 if (dbg_hc(chan)) 1685 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1686 } 1687 1688 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 1689 chan->halt_status = halt_status; 1690 1691 if (hcchar & HCCHAR_CHENA) { 1692 if (dbg_hc(chan)) 1693 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1694 chan->halt_pending = 1; 1695 chan->halt_on_queue = 0; 1696 } else { 1697 if (dbg_hc(chan)) 1698 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1699 chan->halt_on_queue = 1; 1700 } 1701 1702 if (dbg_hc(chan)) { 1703 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1704 chan->hc_num); 1705 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1706 hcchar); 1707 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1708 chan->halt_pending); 1709 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1710 chan->halt_on_queue); 1711 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1712 chan->halt_status); 1713 } 1714 } 1715 1716 /** 1717 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1718 * 1719 * @hsotg: Programming view of DWC_otg controller 1720 * @chan: Identifies the host channel to clean up 1721 * 1722 * This function is normally called after a transfer is done and the host 1723 * channel is being released 1724 */ 1725 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1726 { 1727 u32 hcintmsk; 1728 1729 chan->xfer_started = 0; 1730 1731 /* 1732 * Clear channel interrupt enables and any unhandled channel interrupt 1733 * conditions 1734 */ 1735 DWC2_WRITE_4(hsotg, HCINTMSK(chan->hc_num), 0); 1736 hcintmsk = 0xffffffff; 1737 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1738 DWC2_WRITE_4(hsotg, HCINT(chan->hc_num), hcintmsk); 1739 } 1740 1741 /** 1742 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1743 * which frame a periodic transfer should occur 1744 * 1745 * @hsotg: Programming view of DWC_otg controller 1746 * @chan: Identifies the host channel to set up and its properties 1747 * @hcchar: Current value of the HCCHAR register for the specified host channel 1748 * 1749 * This function has no effect on non-periodic transfers 1750 */ 1751 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1752 struct dwc2_host_chan *chan, u32 *hcchar) 1753 { 1754 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1755 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1756 /* 1 if _next_ frame is odd, 0 if it's even */ 1757 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1)) 1758 *hcchar |= HCCHAR_ODDFRM; 1759 } 1760 } 1761 1762 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1763 { 1764 /* Set up the initial PID for the transfer */ 1765 if (chan->speed == USB_SPEED_HIGH) { 1766 if (chan->ep_is_in) { 1767 if (chan->multi_count == 1) 1768 chan->data_pid_start = DWC2_HC_PID_DATA0; 1769 else if (chan->multi_count == 2) 1770 chan->data_pid_start = DWC2_HC_PID_DATA1; 1771 else 1772 chan->data_pid_start = DWC2_HC_PID_DATA2; 1773 } else { 1774 if (chan->multi_count == 1) 1775 chan->data_pid_start = DWC2_HC_PID_DATA0; 1776 else 1777 chan->data_pid_start = DWC2_HC_PID_MDATA; 1778 } 1779 } else { 1780 chan->data_pid_start = DWC2_HC_PID_DATA0; 1781 } 1782 } 1783 1784 /** 1785 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1786 * the Host Channel 1787 * 1788 * @hsotg: Programming view of DWC_otg controller 1789 * @chan: Information needed to initialize the host channel 1790 * 1791 * This function should only be called in Slave mode. For a channel associated 1792 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1793 * associated with a periodic EP, the periodic Tx FIFO is written. 1794 * 1795 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1796 * the number of bytes written to the Tx FIFO. 1797 */ 1798 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1799 struct dwc2_host_chan *chan) 1800 { 1801 u32 i; 1802 u32 remaining_count; 1803 u32 byte_count; 1804 u32 dword_count; 1805 u32 *data_buf = (u32 *)chan->xfer_buf; 1806 u32 data_fifo; 1807 1808 if (dbg_hc(chan)) 1809 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1810 1811 data_fifo = HCFIFO(chan->hc_num); 1812 1813 remaining_count = chan->xfer_len - chan->xfer_count; 1814 if (remaining_count > chan->max_packet) 1815 byte_count = chan->max_packet; 1816 else 1817 byte_count = remaining_count; 1818 1819 dword_count = (byte_count + 3) / 4; 1820 1821 if (((unsigned long)data_buf & 0x3) == 0) { 1822 /* xfer_buf is DWORD aligned */ 1823 for (i = 0; i < dword_count; i++, data_buf++) 1824 DWC2_WRITE_4(hsotg, data_fifo, *data_buf); 1825 } else { 1826 /* xfer_buf is not DWORD aligned */ 1827 for (i = 0; i < dword_count; i++, data_buf++) { 1828 u32 data = data_buf[0] | data_buf[1] << 8 | 1829 data_buf[2] << 16 | data_buf[3] << 24; 1830 DWC2_WRITE_4(hsotg, data_fifo, data); 1831 } 1832 } 1833 1834 chan->xfer_count += byte_count; 1835 chan->xfer_buf += byte_count; 1836 } 1837 1838 /** 1839 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1840 * channel and starts the transfer 1841 * 1842 * @hsotg: Programming view of DWC_otg controller 1843 * @chan: Information needed to initialize the host channel. The xfer_len value 1844 * may be reduced to accommodate the max widths of the XferSize and 1845 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1846 * changed to reflect the final xfer_len value. 1847 * 1848 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1849 * the caller must ensure that there is sufficient space in the request queue 1850 * and Tx Data FIFO. 1851 * 1852 * For an OUT transfer in Slave mode, it loads a data packet into the 1853 * appropriate FIFO. If necessary, additional data packets are loaded in the 1854 * Host ISR. 1855 * 1856 * For an IN transfer in Slave mode, a data packet is requested. The data 1857 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1858 * additional data packets are requested in the Host ISR. 1859 * 1860 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1861 * register along with a packet count of 1 and the channel is enabled. This 1862 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1863 * simply set to 0 since no data transfer occurs in this case. 1864 * 1865 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1866 * all the information required to perform the subsequent data transfer. In 1867 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1868 * controller performs the entire PING protocol, then starts the data 1869 * transfer. 1870 */ 1871 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1872 struct dwc2_host_chan *chan) 1873 { 1874 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; 1875 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; 1876 u32 hcchar; 1877 u32 hctsiz = 0; 1878 u16 num_packets; 1879 u32 ec_mc; 1880 1881 if (dbg_hc(chan)) 1882 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1883 1884 if (chan->do_ping) { 1885 if (hsotg->core_params->dma_enable <= 0) { 1886 if (dbg_hc(chan)) 1887 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1888 dwc2_hc_do_ping(hsotg, chan); 1889 chan->xfer_started = 1; 1890 return; 1891 } else { 1892 if (dbg_hc(chan)) 1893 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1894 hctsiz |= TSIZ_DOPNG; 1895 } 1896 } 1897 1898 if (chan->do_split) { 1899 if (dbg_hc(chan)) 1900 dev_vdbg(hsotg->dev, "split\n"); 1901 num_packets = 1; 1902 1903 if (chan->complete_split && !chan->ep_is_in) 1904 /* 1905 * For CSPLIT OUT Transfer, set the size to 0 so the 1906 * core doesn't expect any data written to the FIFO 1907 */ 1908 chan->xfer_len = 0; 1909 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1910 chan->xfer_len = chan->max_packet; 1911 else if (!chan->ep_is_in && chan->xfer_len > 188) 1912 chan->xfer_len = 188; 1913 1914 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1915 TSIZ_XFERSIZE_MASK; 1916 1917 /* For split set ec_mc for immediate retries */ 1918 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1919 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1920 ec_mc = 3; 1921 else 1922 ec_mc = 1; 1923 } else { 1924 if (dbg_hc(chan)) 1925 dev_vdbg(hsotg->dev, "no split\n"); 1926 /* 1927 * Ensure that the transfer length and packet count will fit 1928 * in the widths allocated for them in the HCTSIZn register 1929 */ 1930 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1931 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1932 /* 1933 * Make sure the transfer size is no larger than one 1934 * (micro)frame's worth of data. (A check was done 1935 * when the periodic transfer was accepted to ensure 1936 * that a (micro)frame's worth of data can be 1937 * programmed into a channel.) 1938 */ 1939 u32 max_periodic_len = 1940 chan->multi_count * chan->max_packet; 1941 1942 if (chan->xfer_len > max_periodic_len) 1943 chan->xfer_len = max_periodic_len; 1944 } else if (chan->xfer_len > max_hc_xfer_size) { 1945 /* 1946 * Make sure that xfer_len is a multiple of max packet 1947 * size 1948 */ 1949 chan->xfer_len = 1950 max_hc_xfer_size - chan->max_packet + 1; 1951 } 1952 1953 if (chan->xfer_len > 0) { 1954 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1955 chan->max_packet; 1956 if (num_packets > max_hc_pkt_count) { 1957 num_packets = max_hc_pkt_count; 1958 chan->xfer_len = num_packets * chan->max_packet; 1959 } 1960 } else { 1961 /* Need 1 packet for transfer length of 0 */ 1962 num_packets = 1; 1963 } 1964 1965 if (chan->ep_is_in) 1966 /* 1967 * Always program an integral # of max packets for IN 1968 * transfers 1969 */ 1970 chan->xfer_len = num_packets * chan->max_packet; 1971 1972 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1973 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1974 /* 1975 * Make sure that the multi_count field matches the 1976 * actual transfer length 1977 */ 1978 chan->multi_count = num_packets; 1979 1980 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1981 dwc2_set_pid_isoc(chan); 1982 1983 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1984 TSIZ_XFERSIZE_MASK; 1985 1986 /* The ec_mc gets the multi_count for non-split */ 1987 ec_mc = chan->multi_count; 1988 } 1989 1990 chan->start_pkt_count = num_packets; 1991 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1992 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1993 TSIZ_SC_MC_PID_MASK; 1994 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 1995 if (dbg_hc(chan)) { 1996 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1997 hctsiz, chan->hc_num); 1998 1999 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 2000 chan->hc_num); 2001 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 2002 (hctsiz & TSIZ_XFERSIZE_MASK) >> 2003 TSIZ_XFERSIZE_SHIFT); 2004 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 2005 (hctsiz & TSIZ_PKTCNT_MASK) >> 2006 TSIZ_PKTCNT_SHIFT); 2007 dev_vdbg(hsotg->dev, " Start PID: %d\n", 2008 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 2009 TSIZ_SC_MC_PID_SHIFT); 2010 } 2011 2012 if (hsotg->core_params->dma_enable > 0) { 2013 dma_addr_t dma_addr; 2014 2015 if (chan->align_buf) { 2016 if (dbg_hc(chan)) 2017 dev_vdbg(hsotg->dev, "align_buf\n"); 2018 dma_addr = chan->align_buf; 2019 } else { 2020 dma_addr = chan->xfer_dma; 2021 } 2022 if (hsotg->hsotg_sc->sc_set_dma_addr == NULL) { 2023 DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num), 2024 (u32)dma_addr); 2025 if (dbg_hc(chan)) 2026 dev_vdbg(hsotg->dev, 2027 "Wrote %08lx to HCDMA(%d)\n", 2028 (unsigned long)dma_addr, 2029 chan->hc_num); 2030 } else { 2031 (void)(*hsotg->hsotg_sc->sc_set_dma_addr)( 2032 hsotg->dev, dma_addr, chan->hc_num); 2033 } 2034 } 2035 2036 /* Start the split */ 2037 if (chan->do_split) { 2038 u32 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 2039 2040 hcsplt |= HCSPLT_SPLTENA; 2041 DWC2_WRITE_4(hsotg, HCSPLT(chan->hc_num), hcsplt); 2042 } 2043 2044 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 2045 hcchar &= ~HCCHAR_MULTICNT_MASK; 2046 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 2047 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 2048 2049 if (hcchar & HCCHAR_CHDIS) 2050 dev_warn(hsotg->dev, 2051 "%s: chdis set, channel %d, hcchar 0x%08x\n", 2052 __func__, chan->hc_num, hcchar); 2053 2054 /* Set host channel enable after all other setup is complete */ 2055 hcchar |= HCCHAR_CHENA; 2056 hcchar &= ~HCCHAR_CHDIS; 2057 2058 if (dbg_hc(chan)) 2059 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 2060 (hcchar & HCCHAR_MULTICNT_MASK) >> 2061 HCCHAR_MULTICNT_SHIFT); 2062 2063 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 2064 if (dbg_hc(chan)) 2065 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 2066 chan->hc_num); 2067 2068 chan->xfer_started = 1; 2069 chan->requests++; 2070 2071 if (hsotg->core_params->dma_enable <= 0 && 2072 !chan->ep_is_in && chan->xfer_len > 0) 2073 /* Load OUT packet into the appropriate Tx FIFO */ 2074 dwc2_hc_write_packet(hsotg, chan); 2075 } 2076 2077 /** 2078 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 2079 * host channel and starts the transfer in Descriptor DMA mode 2080 * 2081 * @hsotg: Programming view of DWC_otg controller 2082 * @chan: Information needed to initialize the host channel 2083 * 2084 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 2085 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 2086 * with micro-frame bitmap. 2087 * 2088 * Initializes HCDMA register with descriptor list address and CTD value then 2089 * starts the transfer via enabling the channel. 2090 */ 2091 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 2092 struct dwc2_host_chan *chan) 2093 { 2094 u32 hcchar; 2095 u32 hctsiz = 0; 2096 2097 if (chan->do_ping) 2098 hctsiz |= TSIZ_DOPNG; 2099 2100 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2101 dwc2_set_pid_isoc(chan); 2102 2103 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 2104 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 2105 TSIZ_SC_MC_PID_MASK; 2106 2107 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 2108 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 2109 2110 /* Non-zero only for high-speed interrupt endpoints */ 2111 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 2112 2113 if (dbg_hc(chan)) { 2114 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 2115 chan->hc_num); 2116 dev_vdbg(hsotg->dev, " Start PID: %d\n", 2117 chan->data_pid_start); 2118 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 2119 } 2120 2121 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 2122 2123 usb_syncmem(&chan->desc_list_usbdma, 0, chan->desc_list_sz, 2124 BUS_DMASYNC_PREWRITE); 2125 2126 if (hsotg->hsotg_sc->sc_set_dma_addr == NULL) { 2127 DWC2_WRITE_4(hsotg, HCDMA(chan->hc_num), chan->desc_list_addr); 2128 if (dbg_hc(chan)) 2129 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 2130 &chan->desc_list_addr, chan->hc_num); 2131 } else { 2132 (void)(*hsotg->hsotg_sc->sc_set_dma_addr)( 2133 hsotg->dev, chan->desc_list_addr, chan->hc_num); 2134 if (dbg_hc(chan)) 2135 dev_vdbg(hsotg->dev, "Wrote %pad to ext dma(%d)\n", 2136 &chan->desc_list_addr, chan->hc_num); 2137 } 2138 2139 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 2140 hcchar &= ~HCCHAR_MULTICNT_MASK; 2141 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 2142 HCCHAR_MULTICNT_MASK; 2143 2144 if (hcchar & HCCHAR_CHDIS) 2145 dev_warn(hsotg->dev, 2146 "%s: chdis set, channel %d, hcchar 0x%08x\n", 2147 __func__, chan->hc_num, hcchar); 2148 2149 /* Set host channel enable after all other setup is complete */ 2150 hcchar |= HCCHAR_CHENA; 2151 hcchar &= ~HCCHAR_CHDIS; 2152 2153 if (dbg_hc(chan)) 2154 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 2155 (hcchar & HCCHAR_MULTICNT_MASK) >> 2156 HCCHAR_MULTICNT_SHIFT); 2157 2158 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 2159 if (dbg_hc(chan)) 2160 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 2161 chan->hc_num); 2162 2163 chan->xfer_started = 1; 2164 chan->requests++; 2165 } 2166 2167 /** 2168 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 2169 * a previous call to dwc2_hc_start_transfer() 2170 * 2171 * @hsotg: Programming view of DWC_otg controller 2172 * @chan: Information needed to initialize the host channel 2173 * 2174 * The caller must ensure there is sufficient space in the request queue and Tx 2175 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 2176 * the controller acts autonomously to complete transfers programmed to a host 2177 * channel. 2178 * 2179 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 2180 * if there is any data remaining to be queued. For an IN transfer, another 2181 * data packet is always requested. For the SETUP phase of a control transfer, 2182 * this function does nothing. 2183 * 2184 * Return: 1 if a new request is queued, 0 if no more requests are required 2185 * for this transfer 2186 */ 2187 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 2188 struct dwc2_host_chan *chan) 2189 { 2190 if (dbg_hc(chan)) 2191 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 2192 chan->hc_num); 2193 2194 if (chan->do_split) 2195 /* SPLITs always queue just once per channel */ 2196 return 0; 2197 2198 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 2199 /* SETUPs are queued only once since they can't be NAK'd */ 2200 return 0; 2201 2202 if (chan->ep_is_in) { 2203 /* 2204 * Always queue another request for other IN transfers. If 2205 * back-to-back INs are issued and NAKs are received for both, 2206 * the driver may still be processing the first NAK when the 2207 * second NAK is received. When the interrupt handler clears 2208 * the NAK interrupt for the first NAK, the second NAK will 2209 * not be seen. So we can't depend on the NAK interrupt 2210 * handler to requeue a NAK'd request. Instead, IN requests 2211 * are issued each time this function is called. When the 2212 * transfer completes, the extra requests for the channel will 2213 * be flushed. 2214 */ 2215 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 2216 2217 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 2218 hcchar |= HCCHAR_CHENA; 2219 hcchar &= ~HCCHAR_CHDIS; 2220 if (dbg_hc(chan)) 2221 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 2222 hcchar); 2223 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 2224 chan->requests++; 2225 return 1; 2226 } 2227 2228 /* OUT transfers */ 2229 2230 if (chan->xfer_count < chan->xfer_len) { 2231 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2232 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2233 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 2234 2235 dwc2_hc_set_even_odd_frame(hsotg, chan, 2236 &hcchar); 2237 } 2238 2239 /* Load OUT packet into the appropriate Tx FIFO */ 2240 dwc2_hc_write_packet(hsotg, chan); 2241 chan->requests++; 2242 return 1; 2243 } 2244 2245 return 0; 2246 } 2247 2248 /** 2249 * dwc2_hc_do_ping() - Starts a PING transfer 2250 * 2251 * @hsotg: Programming view of DWC_otg controller 2252 * @chan: Information needed to initialize the host channel 2253 * 2254 * This function should only be called in Slave mode. The Do Ping bit is set in 2255 * the HCTSIZ register, then the channel is enabled. 2256 */ 2257 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 2258 { 2259 u32 hcchar; 2260 u32 hctsiz; 2261 2262 if (dbg_hc(chan)) 2263 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 2264 chan->hc_num); 2265 2266 2267 hctsiz = TSIZ_DOPNG; 2268 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 2269 DWC2_WRITE_4(hsotg, HCTSIZ(chan->hc_num), hctsiz); 2270 2271 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 2272 hcchar |= HCCHAR_CHENA; 2273 hcchar &= ~HCCHAR_CHDIS; 2274 DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar); 2275 } 2276 2277 /** 2278 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 2279 * the HFIR register according to PHY type and speed 2280 * 2281 * @hsotg: Programming view of DWC_otg controller 2282 * 2283 * NOTE: The caller can modify the value of the HFIR register only after the 2284 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 2285 * has been set 2286 */ 2287 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 2288 { 2289 u32 usbcfg; 2290 u32 hprt0; 2291 int clock = 60; /* default value */ 2292 2293 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 2294 hprt0 = DWC2_READ_4(hsotg, HPRT0); 2295 2296 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 2297 !(usbcfg & GUSBCFG_PHYIF16)) 2298 clock = 60; 2299 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 2300 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 2301 clock = 48; 2302 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 2303 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 2304 clock = 30; 2305 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 2306 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 2307 clock = 60; 2308 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 2309 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 2310 clock = 48; 2311 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 2312 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 2313 clock = 48; 2314 if ((usbcfg & GUSBCFG_PHYSEL) && 2315 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 2316 clock = 48; 2317 2318 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 2319 /* High speed case */ 2320 return 125 * clock - 1; 2321 else 2322 /* FS/LS case */ 2323 return 1000 * clock - 1; 2324 } 2325 2326 /** 2327 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 2328 * buffer 2329 * 2330 * @core_if: Programming view of DWC_otg controller 2331 * @dest: Destination buffer for the packet 2332 * @bytes: Number of bytes to copy to the destination 2333 */ 2334 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 2335 { 2336 bus_size_t fifo = HCFIFO(0); 2337 u32 *data_buf = (u32 *)dest; 2338 int word_count = (bytes + 3) / 4; 2339 int i; 2340 2341 /* 2342 * Todo: Account for the case where dest is not dword aligned. This 2343 * requires reading data from the FIFO into a u32 temp buffer, then 2344 * moving it into the data buffer. 2345 */ 2346 2347 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 2348 2349 for (i = 0; i < word_count; i++, data_buf++) 2350 *data_buf = DWC2_READ_4(hsotg, fifo); 2351 } 2352 2353 /** 2354 * dwc2_dump_host_registers() - Prints the host registers 2355 * 2356 * @hsotg: Programming view of DWC_otg controller 2357 * 2358 * NOTE: This function will be removed once the peripheral controller code 2359 * is integrated and the driver is stable 2360 */ 2361 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 2362 { 2363 #ifdef DWC2_DEBUG 2364 bus_size_t addr; 2365 int i; 2366 2367 dev_dbg(hsotg->dev, "Host Global Registers\n"); 2368 addr = HCFG; 2369 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 2370 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2371 addr = HFIR; 2372 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 2373 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2374 addr = HFNUM; 2375 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 2376 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2377 addr = HPTXSTS; 2378 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 2379 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2380 addr = HAINT; 2381 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 2382 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2383 addr = HAINTMSK; 2384 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 2385 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2386 if (hsotg->core_params->dma_desc_enable > 0) { 2387 addr = HFLBADDR; 2388 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 2389 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2390 } 2391 2392 addr = HPRT0; 2393 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 2394 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2395 2396 for (i = 0; i < hsotg->core_params->host_channels; i++) { 2397 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 2398 addr = HCCHAR(i); 2399 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 2400 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2401 addr = HCSPLT(i); 2402 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 2403 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2404 addr = HCINT(i); 2405 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 2406 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2407 addr = HCINTMSK(i); 2408 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 2409 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2410 addr = HCTSIZ(i); 2411 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 2412 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2413 addr = HCDMA(i); 2414 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 2415 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2416 if (hsotg->core_params->dma_desc_enable > 0) { 2417 addr = HCDMAB(i); 2418 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 2419 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2420 } 2421 } 2422 #endif 2423 } 2424 2425 /** 2426 * dwc2_dump_global_registers() - Prints the core global registers 2427 * 2428 * @hsotg: Programming view of DWC_otg controller 2429 * 2430 * NOTE: This function will be removed once the peripheral controller code 2431 * is integrated and the driver is stable 2432 */ 2433 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 2434 { 2435 #ifdef DWC2_DEBUG 2436 bus_size_t addr; 2437 2438 dev_dbg(hsotg->dev, "Core Global Registers\n"); 2439 addr = GOTGCTL; 2440 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 2441 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2442 addr = GOTGINT; 2443 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 2444 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2445 addr = GAHBCFG; 2446 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 2447 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2448 addr = GUSBCFG; 2449 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 2450 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2451 addr = GRSTCTL; 2452 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 2453 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2454 addr = GINTSTS; 2455 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 2456 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2457 addr = GINTMSK; 2458 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 2459 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2460 addr = GRXSTSR; 2461 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 2462 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2463 addr = GRXFSIZ; 2464 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 2465 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2466 addr = GNPTXFSIZ; 2467 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 2468 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2469 addr = GNPTXSTS; 2470 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 2471 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2472 addr = GI2CCTL; 2473 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 2474 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2475 addr = GPVNDCTL; 2476 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 2477 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2478 addr = GGPIO; 2479 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 2480 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2481 addr = GUID; 2482 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 2483 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2484 addr = GSNPSID; 2485 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 2486 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2487 addr = GHWCFG1; 2488 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 2489 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2490 addr = GHWCFG2; 2491 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 2492 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2493 addr = GHWCFG3; 2494 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 2495 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2496 addr = GHWCFG4; 2497 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 2498 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2499 addr = GLPMCFG; 2500 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 2501 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2502 addr = GPWRDN; 2503 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 2504 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2505 addr = GDFIFOCFG; 2506 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 2507 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2508 addr = HPTXFSIZ; 2509 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 2510 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2511 2512 addr = PCGCTL; 2513 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 2514 (unsigned long)addr, DWC2_READ_4(hsotg, addr)); 2515 #endif 2516 } 2517 2518 /** 2519 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 2520 * 2521 * @hsotg: Programming view of DWC_otg controller 2522 * @num: Tx FIFO to flush 2523 */ 2524 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 2525 { 2526 u32 greset; 2527 int count = 0; 2528 2529 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 2530 2531 greset = GRSTCTL_TXFFLSH; 2532 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 2533 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 2534 2535 do { 2536 greset = DWC2_READ_4(hsotg, GRSTCTL); 2537 if (++count > 10000) { 2538 dev_warn(hsotg->dev, 2539 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", 2540 __func__, greset, 2541 DWC2_READ_4(hsotg, GNPTXSTS)); 2542 break; 2543 } 2544 udelay(1); 2545 } while (greset & GRSTCTL_TXFFLSH); 2546 2547 /* Wait for at least 3 PHY Clocks */ 2548 udelay(1); 2549 } 2550 2551 /** 2552 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 2553 * 2554 * @hsotg: Programming view of DWC_otg controller 2555 */ 2556 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 2557 { 2558 u32 greset; 2559 int count = 0; 2560 2561 dev_vdbg(hsotg->dev, "%s()\n", __func__); 2562 2563 greset = GRSTCTL_RXFFLSH; 2564 DWC2_WRITE_4(hsotg, GRSTCTL, greset); 2565 2566 do { 2567 greset = DWC2_READ_4(hsotg, GRSTCTL); 2568 if (++count > 10000) { 2569 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", 2570 __func__, greset); 2571 break; 2572 } 2573 udelay(1); 2574 } while (greset & GRSTCTL_RXFFLSH); 2575 2576 /* Wait for at least 3 PHY Clocks */ 2577 udelay(1); 2578 } 2579 2580 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) 2581 2582 /* Parameter access functions */ 2583 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 2584 { 2585 int valid = 1; 2586 2587 switch (val) { 2588 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 2589 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 2590 valid = 0; 2591 break; 2592 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 2593 switch (hsotg->hw_params.op_mode) { 2594 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 2595 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 2596 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 2597 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 2598 break; 2599 default: 2600 valid = 0; 2601 break; 2602 } 2603 break; 2604 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 2605 /* always valid */ 2606 break; 2607 default: 2608 valid = 0; 2609 break; 2610 } 2611 2612 if (!valid) { 2613 if (val >= 0) 2614 dev_err(hsotg->dev, 2615 "%d invalid for otg_cap parameter. Check HW configuration.\n", 2616 val); 2617 switch (hsotg->hw_params.op_mode) { 2618 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 2619 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 2620 break; 2621 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 2622 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 2623 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 2624 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 2625 break; 2626 default: 2627 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 2628 break; 2629 } 2630 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); 2631 } 2632 2633 hsotg->core_params->otg_cap = val; 2634 } 2635 2636 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 2637 { 2638 int valid = 1; 2639 2640 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) 2641 valid = 0; 2642 if (val < 0) 2643 valid = 0; 2644 2645 if (!valid) { 2646 if (val >= 0) 2647 dev_err(hsotg->dev, 2648 "%d invalid for dma_enable parameter. Check HW configuration.\n", 2649 val); 2650 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; 2651 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); 2652 } 2653 2654 hsotg->core_params->dma_enable = val; 2655 } 2656 2657 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 2658 { 2659 int valid = 1; 2660 2661 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 2662 !hsotg->hw_params.dma_desc_enable)) 2663 valid = 0; 2664 if (val < 0) 2665 valid = 0; 2666 2667 if (!valid) { 2668 if (val >= 0) 2669 dev_err(hsotg->dev, 2670 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", 2671 val); 2672 val = (hsotg->core_params->dma_enable > 0 && 2673 hsotg->hw_params.dma_desc_enable); 2674 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); 2675 } 2676 2677 hsotg->core_params->dma_desc_enable = val; 2678 } 2679 2680 void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val) 2681 { 2682 int valid = 1; 2683 2684 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 2685 !hsotg->hw_params.dma_desc_enable)) 2686 valid = 0; 2687 if (val < 0) 2688 valid = 0; 2689 2690 if (!valid) { 2691 if (val >= 0) 2692 dev_err(hsotg->dev, 2693 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n", 2694 val); 2695 val = (hsotg->core_params->dma_enable > 0 && 2696 hsotg->hw_params.dma_desc_enable); 2697 } 2698 2699 hsotg->core_params->dma_desc_fs_enable = val; 2700 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val); 2701 } 2702 2703 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 2704 int val) 2705 { 2706 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2707 if (val >= 0) { 2708 dev_err(hsotg->dev, 2709 "Wrong value for host_support_fs_low_power\n"); 2710 dev_err(hsotg->dev, 2711 "host_support_fs_low_power must be 0 or 1\n"); 2712 } 2713 val = 0; 2714 dev_dbg(hsotg->dev, 2715 "Setting host_support_fs_low_power to %d\n", val); 2716 } 2717 2718 hsotg->core_params->host_support_fs_ls_low_power = val; 2719 } 2720 2721 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) 2722 { 2723 int valid = 1; 2724 2725 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 2726 valid = 0; 2727 if (val < 0) 2728 valid = 0; 2729 2730 if (!valid) { 2731 if (val >= 0) 2732 dev_err(hsotg->dev, 2733 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", 2734 val); 2735 val = hsotg->hw_params.enable_dynamic_fifo; 2736 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); 2737 } 2738 2739 hsotg->core_params->enable_dynamic_fifo = val; 2740 } 2741 2742 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2743 { 2744 int valid = 1; 2745 2746 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) 2747 valid = 0; 2748 2749 if (!valid) { 2750 if (val >= 0) 2751 dev_err(hsotg->dev, 2752 "%d invalid for host_rx_fifo_size. Check HW configuration.\n", 2753 val); 2754 val = hsotg->hw_params.host_rx_fifo_size; 2755 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); 2756 } 2757 2758 hsotg->core_params->host_rx_fifo_size = val; 2759 } 2760 2761 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2762 { 2763 int valid = 1; 2764 2765 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 2766 valid = 0; 2767 2768 if (!valid) { 2769 if (val >= 0) 2770 dev_err(hsotg->dev, 2771 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", 2772 val); 2773 val = hsotg->hw_params.host_nperio_tx_fifo_size; 2774 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", 2775 val); 2776 } 2777 2778 hsotg->core_params->host_nperio_tx_fifo_size = val; 2779 } 2780 2781 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2782 { 2783 int valid = 1; 2784 2785 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 2786 valid = 0; 2787 2788 if (!valid) { 2789 if (val >= 0) 2790 dev_err(hsotg->dev, 2791 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 2792 val); 2793 val = hsotg->hw_params.host_perio_tx_fifo_size; 2794 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 2795 val); 2796 } 2797 2798 hsotg->core_params->host_perio_tx_fifo_size = val; 2799 } 2800 2801 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 2802 { 2803 int valid = 1; 2804 2805 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) 2806 valid = 0; 2807 2808 if (!valid) { 2809 if (val >= 0) 2810 dev_err(hsotg->dev, 2811 "%d invalid for max_transfer_size. Check HW configuration.\n", 2812 val); 2813 val = hsotg->hw_params.max_transfer_size; 2814 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 2815 } 2816 2817 hsotg->core_params->max_transfer_size = val; 2818 } 2819 2820 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 2821 { 2822 int valid = 1; 2823 2824 if (val < 15 || val > hsotg->hw_params.max_packet_count) 2825 valid = 0; 2826 2827 if (!valid) { 2828 if (val >= 0) 2829 dev_err(hsotg->dev, 2830 "%d invalid for max_packet_count. Check HW configuration.\n", 2831 val); 2832 val = hsotg->hw_params.max_packet_count; 2833 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 2834 } 2835 2836 hsotg->core_params->max_packet_count = val; 2837 } 2838 2839 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 2840 { 2841 int valid = 1; 2842 2843 if (val < 1 || val > hsotg->hw_params.host_channels) 2844 valid = 0; 2845 2846 if (!valid) { 2847 if (val >= 0) 2848 dev_err(hsotg->dev, 2849 "%d invalid for host_channels. Check HW configuration.\n", 2850 val); 2851 val = hsotg->hw_params.host_channels; 2852 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); 2853 } 2854 2855 hsotg->core_params->host_channels = val; 2856 } 2857 2858 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 2859 { 2860 int valid = 0; 2861 u32 hs_phy_type, fs_phy_type; 2862 2863 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, 2864 DWC2_PHY_TYPE_PARAM_ULPI)) { 2865 if (val >= 0) { 2866 dev_err(hsotg->dev, "Wrong value for phy_type\n"); 2867 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); 2868 } 2869 2870 valid = 0; 2871 } 2872 2873 hs_phy_type = hsotg->hw_params.hs_phy_type; 2874 fs_phy_type = hsotg->hw_params.fs_phy_type; 2875 if (val == DWC2_PHY_TYPE_PARAM_UTMI && 2876 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2877 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2878 valid = 1; 2879 else if (val == DWC2_PHY_TYPE_PARAM_ULPI && 2880 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || 2881 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2882 valid = 1; 2883 else if (val == DWC2_PHY_TYPE_PARAM_FS && 2884 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 2885 valid = 1; 2886 2887 if (!valid) { 2888 if (val >= 0) 2889 dev_err(hsotg->dev, 2890 "%d invalid for phy_type. Check HW configuration.\n", 2891 val); 2892 val = DWC2_PHY_TYPE_PARAM_FS; 2893 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 2894 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2895 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 2896 val = DWC2_PHY_TYPE_PARAM_UTMI; 2897 else 2898 val = DWC2_PHY_TYPE_PARAM_ULPI; 2899 } 2900 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 2901 } 2902 2903 hsotg->core_params->phy_type = val; 2904 } 2905 2906 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) 2907 { 2908 return hsotg->core_params->phy_type; 2909 } 2910 2911 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) 2912 { 2913 int valid = 1; 2914 2915 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2916 if (val >= 0) { 2917 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); 2918 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); 2919 } 2920 valid = 0; 2921 } 2922 2923 if (val == DWC2_SPEED_PARAM_HIGH && 2924 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2925 valid = 0; 2926 2927 if (!valid) { 2928 if (val >= 0) 2929 dev_err(hsotg->dev, 2930 "%d invalid for speed parameter. Check HW configuration.\n", 2931 val); 2932 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 2933 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 2934 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 2935 } 2936 2937 hsotg->core_params->speed = val; 2938 } 2939 2940 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) 2941 { 2942 int valid = 1; 2943 2944 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 2945 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 2946 if (val >= 0) { 2947 dev_err(hsotg->dev, 2948 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 2949 dev_err(hsotg->dev, 2950 "host_ls_low_power_phy_clk must be 0 or 1\n"); 2951 } 2952 valid = 0; 2953 } 2954 2955 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && 2956 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2957 valid = 0; 2958 2959 if (!valid) { 2960 if (val >= 0) 2961 dev_err(hsotg->dev, 2962 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", 2963 val); 2964 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS 2965 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 2966 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; 2967 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", 2968 val); 2969 } 2970 2971 hsotg->core_params->host_ls_low_power_phy_clk = val; 2972 } 2973 2974 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) 2975 { 2976 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2977 if (val >= 0) { 2978 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); 2979 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); 2980 } 2981 val = 0; 2982 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); 2983 } 2984 2985 hsotg->core_params->phy_ulpi_ddr = val; 2986 } 2987 2988 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) 2989 { 2990 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2991 if (val >= 0) { 2992 dev_err(hsotg->dev, 2993 "Wrong value for phy_ulpi_ext_vbus\n"); 2994 dev_err(hsotg->dev, 2995 "phy_ulpi_ext_vbus must be 0 or 1\n"); 2996 } 2997 val = 0; 2998 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); 2999 } 3000 3001 hsotg->core_params->phy_ulpi_ext_vbus = val; 3002 } 3003 3004 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 3005 { 3006 int valid = 0; 3007 3008 switch (hsotg->hw_params.utmi_phy_data_width) { 3009 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 3010 valid = (val == 8); 3011 break; 3012 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 3013 valid = (val == 16); 3014 break; 3015 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 3016 valid = (val == 8 || val == 16); 3017 break; 3018 } 3019 3020 if (!valid) { 3021 if (val >= 0) { 3022 dev_err(hsotg->dev, 3023 "%d invalid for phy_utmi_width. Check HW configuration.\n", 3024 val); 3025 } 3026 val = (hsotg->hw_params.utmi_phy_data_width == 3027 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 3028 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); 3029 } 3030 3031 hsotg->core_params->phy_utmi_width = val; 3032 } 3033 3034 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) 3035 { 3036 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3037 if (val >= 0) { 3038 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); 3039 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); 3040 } 3041 val = 0; 3042 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); 3043 } 3044 3045 hsotg->core_params->ulpi_fs_ls = val; 3046 } 3047 3048 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) 3049 { 3050 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3051 if (val >= 0) { 3052 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); 3053 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); 3054 } 3055 val = 0; 3056 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); 3057 } 3058 3059 hsotg->core_params->ts_dline = val; 3060 } 3061 3062 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) 3063 { 3064 int valid = 1; 3065 3066 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3067 if (val >= 0) { 3068 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); 3069 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); 3070 } 3071 3072 valid = 0; 3073 } 3074 3075 if (val == 1 && !(hsotg->hw_params.i2c_enable)) 3076 valid = 0; 3077 3078 if (!valid) { 3079 if (val >= 0) 3080 dev_err(hsotg->dev, 3081 "%d invalid for i2c_enable. Check HW configuration.\n", 3082 val); 3083 val = hsotg->hw_params.i2c_enable; 3084 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 3085 } 3086 3087 hsotg->core_params->i2c_enable = val; 3088 } 3089 3090 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) 3091 { 3092 int valid = 1; 3093 3094 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3095 if (val >= 0) { 3096 dev_err(hsotg->dev, 3097 "Wrong value for en_multiple_tx_fifo,\n"); 3098 dev_err(hsotg->dev, 3099 "en_multiple_tx_fifo must be 0 or 1\n"); 3100 } 3101 valid = 0; 3102 } 3103 3104 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) 3105 valid = 0; 3106 3107 if (!valid) { 3108 if (val >= 0) 3109 dev_err(hsotg->dev, 3110 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", 3111 val); 3112 val = hsotg->hw_params.en_multiple_tx_fifo; 3113 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); 3114 } 3115 3116 hsotg->core_params->en_multiple_tx_fifo = val; 3117 } 3118 3119 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 3120 { 3121 int valid = 1; 3122 3123 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3124 if (val >= 0) { 3125 dev_err(hsotg->dev, 3126 "'%d' invalid for parameter reload_ctl\n", val); 3127 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); 3128 } 3129 valid = 0; 3130 } 3131 3132 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) 3133 valid = 0; 3134 3135 if (!valid) { 3136 if (val >= 0) 3137 dev_err(hsotg->dev, 3138 "%d invalid for parameter reload_ctl. Check HW configuration.\n", 3139 val); 3140 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; 3141 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); 3142 } 3143 3144 hsotg->core_params->reload_ctl = val; 3145 } 3146 3147 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 3148 { 3149 if (val != -1) 3150 hsotg->core_params->ahbcfg = val; 3151 else 3152 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << 3153 GAHBCFG_HBSTLEN_SHIFT; 3154 } 3155 3156 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 3157 { 3158 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3159 if (val >= 0) { 3160 dev_err(hsotg->dev, 3161 "'%d' invalid for parameter otg_ver\n", val); 3162 dev_err(hsotg->dev, 3163 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); 3164 } 3165 val = 0; 3166 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); 3167 } 3168 3169 hsotg->core_params->otg_ver = val; 3170 } 3171 3172 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 3173 { 3174 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3175 if (val >= 0) { 3176 dev_err(hsotg->dev, 3177 "'%d' invalid for parameter uframe_sched\n", 3178 val); 3179 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); 3180 } 3181 val = 1; 3182 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); 3183 } 3184 3185 hsotg->core_params->uframe_sched = val; 3186 } 3187 3188 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, 3189 int val) 3190 { 3191 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3192 if (val >= 0) { 3193 dev_err(hsotg->dev, 3194 "'%d' invalid for parameter external_id_pin_ctl\n", 3195 val); 3196 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); 3197 } 3198 val = 0; 3199 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); 3200 } 3201 3202 hsotg->core_params->external_id_pin_ctl = val; 3203 } 3204 3205 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, 3206 int val) 3207 { 3208 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3209 if (val >= 0) { 3210 dev_err(hsotg->dev, 3211 "'%d' invalid for parameter hibernation\n", 3212 val); 3213 dev_err(hsotg->dev, "hibernation must be 0 or 1\n"); 3214 } 3215 val = 0; 3216 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); 3217 } 3218 3219 hsotg->core_params->hibernation = val; 3220 } 3221 3222 /* 3223 * This function is called during module intialization to pass module parameters 3224 * for the DWC_otg core. 3225 */ 3226 void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 3227 const struct dwc2_core_params *params) 3228 { 3229 dev_dbg(hsotg->dev, "%s()\n", __func__); 3230 3231 dwc2_set_param_otg_cap(hsotg, params->otg_cap); 3232 dwc2_set_param_dma_enable(hsotg, params->dma_enable); 3233 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); 3234 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); 3235 dwc2_set_param_host_support_fs_ls_low_power(hsotg, 3236 params->host_support_fs_ls_low_power); 3237 dwc2_set_param_enable_dynamic_fifo(hsotg, 3238 params->enable_dynamic_fifo); 3239 dwc2_set_param_host_rx_fifo_size(hsotg, 3240 params->host_rx_fifo_size); 3241 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 3242 params->host_nperio_tx_fifo_size); 3243 dwc2_set_param_host_perio_tx_fifo_size(hsotg, 3244 params->host_perio_tx_fifo_size); 3245 dwc2_set_param_max_transfer_size(hsotg, 3246 params->max_transfer_size); 3247 dwc2_set_param_max_packet_count(hsotg, 3248 params->max_packet_count); 3249 dwc2_set_param_host_channels(hsotg, params->host_channels); 3250 dwc2_set_param_phy_type(hsotg, params->phy_type); 3251 dwc2_set_param_speed(hsotg, params->speed); 3252 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 3253 params->host_ls_low_power_phy_clk); 3254 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 3255 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 3256 params->phy_ulpi_ext_vbus); 3257 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 3258 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 3259 dwc2_set_param_ts_dline(hsotg, params->ts_dline); 3260 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 3261 dwc2_set_param_en_multiple_tx_fifo(hsotg, 3262 params->en_multiple_tx_fifo); 3263 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 3264 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 3265 dwc2_set_param_otg_ver(hsotg, params->otg_ver); 3266 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); 3267 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); 3268 dwc2_set_param_hibernation(hsotg, params->hibernation); 3269 } 3270 3271 /* 3272 * Forces either host or device mode if the controller is not 3273 * currently in that mode. 3274 * 3275 * Returns true if the mode was forced. 3276 */ 3277 static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host) 3278 { 3279 if (host && dwc2_is_host_mode(hsotg)) 3280 return false; 3281 else if (!host && dwc2_is_device_mode(hsotg)) 3282 return false; 3283 3284 return dwc2_force_mode(hsotg, host); 3285 } 3286 3287 /* 3288 * Gets host hardware parameters. Forces host mode if not currently in 3289 * host mode. Should be called immediately after a core soft reset in 3290 * order to get the reset values. 3291 */ 3292 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 3293 { 3294 struct dwc2_hw_params *hw = &hsotg->hw_params; 3295 u32 gnptxfsiz; 3296 u32 hptxfsiz; 3297 bool forced; 3298 3299 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 3300 return; 3301 3302 forced = dwc2_force_mode_if_needed(hsotg, true); 3303 3304 gnptxfsiz = DWC2_READ_4(hsotg, GNPTXFSIZ); 3305 hptxfsiz = DWC2_READ_4(hsotg, HPTXFSIZ); 3306 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 3307 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 3308 3309 if (forced) 3310 dwc2_clear_force_mode(hsotg); 3311 3312 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 3313 FIFOSIZE_DEPTH_SHIFT; 3314 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 3315 FIFOSIZE_DEPTH_SHIFT; 3316 } 3317 3318 /* 3319 * Gets device hardware parameters. Forces device mode if not 3320 * currently in device mode. Should be called immediately after a core 3321 * soft reset in order to get the reset values. 3322 */ 3323 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 3324 { 3325 struct dwc2_hw_params *hw = &hsotg->hw_params; 3326 bool forced; 3327 u32 gnptxfsiz; 3328 3329 if (hsotg->dr_mode == USB_DR_MODE_HOST) 3330 return; 3331 3332 forced = dwc2_force_mode_if_needed(hsotg, false); 3333 3334 gnptxfsiz = DWC2_READ_4(hsotg, GNPTXFSIZ); 3335 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 3336 3337 if (forced) 3338 dwc2_clear_force_mode(hsotg); 3339 3340 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 3341 FIFOSIZE_DEPTH_SHIFT; 3342 } 3343 3344 /** 3345 * During device initialization, read various hardware configuration 3346 * registers and interpret the contents. 3347 */ 3348 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 3349 { 3350 struct dwc2_hw_params *hw = &hsotg->hw_params; 3351 unsigned width; 3352 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 3353 u32 grxfsiz; 3354 3355 /* 3356 * Attempt to ensure this device is really a DWC_otg Controller. 3357 * Read and verify the GSNPSID register contents. The value should be 3358 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 3359 * as in "OTG version 2.xx" or "OTG version 3.xx". 3360 */ 3361 hw->snpsid = DWC2_READ_4(hsotg, GSNPSID); 3362 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 3363 (hw->snpsid & 0xfffff000) != 0x4f543000) { 3364 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 3365 hw->snpsid); 3366 return -ENODEV; 3367 } 3368 3369 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 3370 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 3371 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 3372 3373 hwcfg1 = DWC2_READ_4(hsotg, GHWCFG1); 3374 hwcfg2 = DWC2_READ_4(hsotg, GHWCFG2); 3375 hwcfg3 = DWC2_READ_4(hsotg, GHWCFG3); 3376 hwcfg4 = DWC2_READ_4(hsotg, GHWCFG4); 3377 grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ); 3378 3379 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); 3380 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 3381 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 3382 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 3383 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 3384 3385 /* 3386 * Host specific hardware parameters. Reading these parameters 3387 * requires the controller to be in host mode. The mode will 3388 * be forced, if necessary, to read these values. 3389 */ 3390 dwc2_get_host_hwparams(hsotg); 3391 dwc2_get_dev_hwparams(hsotg); 3392 3393 /* hwcfg1 */ 3394 hw->dev_ep_dirs = hwcfg1; 3395 3396 /* hwcfg2 */ 3397 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 3398 GHWCFG2_OP_MODE_SHIFT; 3399 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 3400 GHWCFG2_ARCHITECTURE_SHIFT; 3401 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 3402 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 3403 GHWCFG2_NUM_HOST_CHAN_SHIFT); 3404 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 3405 GHWCFG2_HS_PHY_TYPE_SHIFT; 3406 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 3407 GHWCFG2_FS_PHY_TYPE_SHIFT; 3408 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 3409 GHWCFG2_NUM_DEV_EP_SHIFT; 3410 hw->nperio_tx_q_depth = 3411 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 3412 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 3413 hw->host_perio_tx_q_depth = 3414 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 3415 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 3416 hw->dev_token_q_depth = 3417 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 3418 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 3419 3420 /* hwcfg3 */ 3421 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 3422 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 3423 hw->max_transfer_size = (1 << (width + 11)) - 1; 3424 /* 3425 * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates 3426 * coherent buffers with this size, and if it's too large we can 3427 * exhaust the coherent DMA pool. 3428 */ 3429 if (hw->max_transfer_size > 65535) 3430 hw->max_transfer_size = 65535; 3431 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 3432 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 3433 hw->max_packet_count = (1 << (width + 4)) - 1; 3434 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 3435 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 3436 GHWCFG3_DFIFO_DEPTH_SHIFT; 3437 3438 /* hwcfg4 */ 3439 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 3440 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 3441 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 3442 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 3443 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 3444 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 3445 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 3446 3447 /* fifo sizes */ 3448 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 3449 GRXFSIZ_DEPTH_SHIFT; 3450 3451 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 3452 dev_dbg(hsotg->dev, " op_mode=%d\n", 3453 hw->op_mode); 3454 dev_dbg(hsotg->dev, " arch=%d\n", 3455 hw->arch); 3456 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 3457 hw->dma_desc_enable); 3458 dev_dbg(hsotg->dev, " power_optimized=%d\n", 3459 hw->power_optimized); 3460 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 3461 hw->i2c_enable); 3462 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 3463 hw->hs_phy_type); 3464 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 3465 hw->fs_phy_type); 3466 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", 3467 hw->utmi_phy_data_width); 3468 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 3469 hw->num_dev_ep); 3470 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 3471 hw->num_dev_perio_in_ep); 3472 dev_dbg(hsotg->dev, " host_channels=%d\n", 3473 hw->host_channels); 3474 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 3475 hw->max_transfer_size); 3476 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 3477 hw->max_packet_count); 3478 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 3479 hw->nperio_tx_q_depth); 3480 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 3481 hw->host_perio_tx_q_depth); 3482 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 3483 hw->dev_token_q_depth); 3484 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 3485 hw->enable_dynamic_fifo); 3486 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 3487 hw->en_multiple_tx_fifo); 3488 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 3489 hw->total_fifo_size); 3490 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", 3491 hw->host_rx_fifo_size); 3492 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 3493 hw->host_nperio_tx_fifo_size); 3494 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 3495 hw->host_perio_tx_fifo_size); 3496 dev_dbg(hsotg->dev, "\n"); 3497 3498 return 0; 3499 } 3500 3501 /* 3502 * Sets all parameters to the given value. 3503 * 3504 * Assumes that the dwc2_core_params struct contains only integers. 3505 */ 3506 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 3507 { 3508 int *p = (int *)params; 3509 size_t size = sizeof(*params) / sizeof(*p); 3510 int i; 3511 3512 for (i = 0; i < size; i++) 3513 p[i] = value; 3514 } 3515 3516 3517 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) 3518 { 3519 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; 3520 } 3521 3522 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 3523 { 3524 if (DWC2_READ_4(hsotg, GSNPSID) == 0xffffffff) 3525 return false; 3526 else 3527 return true; 3528 } 3529 3530 /** 3531 * dwc2_enable_global_interrupts() - Enables the controller's Global 3532 * Interrupt in the AHB Config register 3533 * 3534 * @hsotg: Programming view of DWC_otg controller 3535 */ 3536 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 3537 { 3538 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 3539 3540 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 3541 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 3542 } 3543 3544 /** 3545 * dwc2_disable_global_interrupts() - Disables the controller's Global 3546 * Interrupt in the AHB Config register 3547 * 3548 * @hsotg: Programming view of DWC_otg controller 3549 */ 3550 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 3551 { 3552 u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 3553 3554 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 3555 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 3556 } 3557 3558 /* Returns the controller's GHWCFG2.OTG_MODE. */ 3559 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg) 3560 { 3561 u32 ghwcfg2 = DWC2_READ_4(hsotg, GHWCFG2); 3562 3563 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 3564 GHWCFG2_OP_MODE_SHIFT; 3565 } 3566 3567 /* Returns true if the controller is capable of DRD. */ 3568 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 3569 { 3570 unsigned op_mode = dwc2_op_mode(hsotg); 3571 3572 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 3573 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 3574 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 3575 } 3576 3577 /* Returns true if the controller is host-only. */ 3578 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 3579 { 3580 unsigned op_mode = dwc2_op_mode(hsotg); 3581 3582 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 3583 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 3584 } 3585 3586 /* Returns true if the controller is device-only. */ 3587 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 3588 { 3589 unsigned op_mode = dwc2_op_mode(hsotg); 3590 3591 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 3592 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 3593 } 3594
Indexes created Tue Sep 29 00:26:59 UTC 2026