| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 163 (s->qos_level_high_wm * frac) / ref_clk_mhz / frac, (s->qos_level_high_wm * frac) / ref_clk_mhz % frac);
183 (s->qos_level_high_wm * frac) / ref_clk_mhz / frac, (s->qos_level_high_wm * frac) / ref_clk_mhz % frac);
316 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
|
| amdgpu_dcn10_hubp.c | 646 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
964 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1028 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
|
| dcn10_hubp.h | 379 HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
586 type QoS_LEVEL_HIGH_WM;\
680 uint32_t qos_level_high_wm; member in struct:dcn_hubp_state
|
| amdgpu_dcn10_hw_sequencer.c | 190 DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
262 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
1697 "qos_level_high_wm: %d, \n"
1711 pipe_ctx->ttu_regs.qos_level_high_wm,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 582 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
587 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
588 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",
589 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubp.c | 151 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
1156 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1220 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1484 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1489 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 344 "DML_RQ_DLG_CALC: qos_level_high_wm = 0x%0x\n",
345 ttu_regs.qos_level_high_wm);
|
| display_mode_structs.h | 473 unsigned int qos_level_high_wm; member in struct:_vcs_dpi_display_ttu_regs_st
|
| amdgpu_dml1_display_rq_dlg_calc.c | 1902 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1904 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 1648 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1650 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 1548 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1550 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
|
| amdgpu_display_rq_dlg_calc_20v2.c | 1549 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1551 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
|
