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    Searched refs:quad_part (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_types.h 59 uint64_t quad_part; member in union:dmub_addr
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hubp.c 338 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
341 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
342 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
345 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
348 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
810 if (address->grph.addr.quad_part == 0) {
815 if (address->grph.meta_addr.quad_part != 0)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
compressor.h 47 uint64_t quad_part; member in union:fbc_physical_address
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hubp.c 381 if (address->grph.addr.quad_part == 0)
388 if (address->grph.meta_addr.quad_part != 0) {
407 if (address->video_progressive.luma_addr.quad_part == 0
408 || address->video_progressive.chroma_addr.quad_part == 0)
417 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
452 if (address->grph_stereo.left_addr.quad_part == 0)
454 if (address->grph_stereo.right_addr.quad_part == 0)
467 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
477 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
742 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part
    [all...]
amdgpu_dcn10_hw_sequencer.c 1832 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
1833 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
1834 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
1876 fb_base.quad_part = (uint64_t)fb_base_value << 24;
1877 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1878 vm0->pte_base.quad_part += fb_base.quad_part;
1879 vm0->pte_base.quad_part -= fb_offset.quad_part;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_debug.c 79 "plane_state->address.grph.addr.quad_part = 0x%"PRIX64";\n"
80 "plane_state->address.grph.meta_addr.quad_part = 0x%"PRIX64";\n"
88 plane_state->address.grph.addr.quad_part,
89 plane_state->address.grph.meta_addr.quad_part,
196 "flip_addr->address.grph.addr.quad_part = 0x%"PRIX64";\n"
197 "flip_addr->address.grph.meta_addr.quad_part = 0x%"PRIX64";\n"
200 update->flip_addr->address.grph.addr.quad_part,
201 update->flip_addr->address.grph.meta_addr.quad_part,
amdgpu_dc_stream.c 289 if (attributes->address.quad_part == 0) {
647 pipe_ctx->stream->dmdata_address.quad_part != 0) {
amdgpu_dc.c 2077 pipe_ctx->stream->dmdata_address.quad_part != 0)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubp.c 60 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
63 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
64 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
74 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
77 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
723 if (address->grph.addr.quad_part == 0)
730 if (address->grph.meta_addr.quad_part != 0)
    [all...]
amdgpu_dcn20_hwseq.c 1082 apt.sys_default.quad_part = 0;
1084 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1085 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1410 && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1861 attr.address.quad_part =
1862 pipe_ctx->stream->dmdata_address.quad_part;
2274 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_srv.c 352 cw0.offset.quad_part = inst_fb->gpu_addr;
356 cw1.offset.quad_part = stack_fb->gpu_addr;
376 cw2.offset.quad_part = data_fb->gpu_addr;
380 cw3.offset.quad_part = bios_fb->gpu_addr;
384 cw4.offset.quad_part = mail_fb->gpu_addr;
391 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
395 cw6.offset.quad_part = fw_state_fb->gpu_addr;
amdgpu_dmub_dcn20.c 80 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
kfd_dbgdev.h 187 unsigned long long quad_part; member in union:ULARGE_INTEGER
kfd_dbgdev.c 143 addr.quad_part = mem_obj->gpu_addr;
243 addr.quad_part = 0;
255 addr.quad_part = (unsigned long long) adw_info->watch_address[index];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_mem_input.c 710 if (address->grph.addr.quad_part == 0)
715 if (address->grph_stereo.left_addr.quad_part == 0 ||
716 address->grph_stereo.right_addr.quad_part == 0)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 58 int64_t quad_part; member in union:large_integer
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 1861 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;

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