1 /* $NetBSD: radeon_dp_mst.c,v 1.5 2021/12/19 09:54:57 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: MIT 4 5 #include <sys/cdefs.h> 6 __KERNEL_RCSID(0, "$NetBSD: radeon_dp_mst.c,v 1.5 2021/12/19 09:54:57 riastradh Exp $"); 7 8 #include <drm/drm_debugfs.h> 9 #include <drm/drm_dp_mst_helper.h> 10 #include <drm/drm_fb_helper.h> 11 #include <drm/drm_file.h> 12 #include <drm/drm_probe_helper.h> 13 14 #include "atom.h" 15 #include "ni_reg.h" 16 #include "radeon.h" 17 18 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector); 19 20 static int radeon_atom_set_enc_offset(int id) 21 { 22 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, 23 EVERGREEN_CRTC1_REGISTER_OFFSET, 24 EVERGREEN_CRTC2_REGISTER_OFFSET, 25 EVERGREEN_CRTC3_REGISTER_OFFSET, 26 EVERGREEN_CRTC4_REGISTER_OFFSET, 27 EVERGREEN_CRTC5_REGISTER_OFFSET, 28 0x13830 - 0x7030 }; 29 30 return offsets[id]; 31 } 32 33 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary, 34 struct radeon_encoder_mst *mst_enc, 35 enum radeon_hpd_id hpd, bool enable) 36 { 37 struct drm_device *dev = primary->base.dev; 38 struct radeon_device *rdev = dev->dev_private; 39 uint32_t reg; 40 int retries = 0; 41 uint32_t temp; 42 43 reg = RREG32(NI_DIG_BE_CNTL + primary->offset); 44 45 /* set MST mode */ 46 reg &= ~NI_DIG_FE_DIG_MODE(7); 47 reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST); 48 49 if (enable) 50 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); 51 else 52 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); 53 54 reg |= NI_DIG_HPD_SELECT(hpd); 55 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); 56 WREG32(NI_DIG_BE_CNTL + primary->offset, reg); 57 58 if (enable) { 59 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); 60 61 do { 62 temp = RREG32(NI_DIG_FE_CNTL + offset); 63 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000); 64 if (retries == 10000) 65 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe); 66 } 67 return 0; 68 } 69 70 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary, 71 int stream_number, 72 int fe, 73 int slots) 74 { 75 struct drm_device *dev = primary->base.dev; 76 struct radeon_device *rdev = dev->dev_private; 77 u32 temp, val; 78 int retries = 0; 79 int satreg, satidx; 80 81 satreg = stream_number >> 1; 82 satidx = stream_number & 1; 83 84 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset); 85 86 val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe); 87 88 val <<= (16 * satidx); 89 90 temp &= ~(0xffff << (16 * satidx)); 91 92 temp |= val; 93 94 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp); 95 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); 96 97 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); 98 99 do { 100 unsigned value1, value2; 101 udelay(10); 102 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); 103 104 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK; 105 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT; 106 107 if (!value1 && !value2) 108 break; 109 } while (retries++ < 50); 110 111 if (retries == 10000) 112 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset); 113 114 /* MTP 16 ? */ 115 return 0; 116 } 117 118 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn, 119 struct radeon_encoder *primary) 120 { 121 struct drm_device *dev = mst_conn->base.dev; 122 struct stream_attribs new_attribs[6]; 123 int i; 124 int idx = 0; 125 struct radeon_connector *radeon_connector; 126 struct drm_connector *connector; 127 128 memset(new_attribs, 0, sizeof(new_attribs)); 129 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 130 struct radeon_encoder *subenc; 131 struct radeon_encoder_mst *mst_enc; 132 133 radeon_connector = to_radeon_connector(connector); 134 if (!radeon_connector->is_mst_connector) 135 continue; 136 137 if (radeon_connector->mst_port != mst_conn) 138 continue; 139 140 subenc = radeon_connector->mst_encoder; 141 mst_enc = subenc->enc_priv; 142 143 if (!mst_enc->enc_active) 144 continue; 145 146 new_attribs[idx].fe = mst_enc->fe; 147 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port); 148 idx++; 149 } 150 151 for (i = 0; i < idx; i++) { 152 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe || 153 new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) { 154 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots); 155 mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe; 156 mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots; 157 } 158 } 159 160 for (i = idx; i < mst_conn->enabled_attribs; i++) { 161 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0); 162 mst_conn->cur_stream_attribs[i].fe = 0; 163 mst_conn->cur_stream_attribs[i].slots = 0; 164 } 165 mst_conn->enabled_attribs = idx; 166 return 0; 167 } 168 169 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp) 170 { 171 struct drm_device *dev = mst->base.dev; 172 struct radeon_device *rdev = dev->dev_private; 173 struct radeon_encoder_mst *mst_enc = mst->enc_priv; 174 uint32_t val, temp; 175 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); 176 int retries = 0; 177 uint32_t x = drm_fixp2int(avg_time_slots_per_mtp); 178 uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26); 179 180 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y); 181 182 WREG32(NI_DP_MSE_RATE_CNTL + offset, val); 183 184 do { 185 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); 186 udelay(10); 187 } while ((temp & 0x1) && (retries++ < 10000)); 188 189 if (retries >= 10000) 190 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe); 191 return 0; 192 } 193 194 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector) 195 { 196 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 197 struct radeon_connector *master = radeon_connector->mst_port; 198 struct edid *edid; 199 int ret = 0; 200 201 edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port); 202 radeon_connector->edid = edid; 203 DRM_DEBUG_KMS("edid retrieved %p\n", edid); 204 if (radeon_connector->edid) { 205 drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 206 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 207 return ret; 208 } 209 drm_connector_update_edid_property(&radeon_connector->base, NULL); 210 211 return ret; 212 } 213 214 static int radeon_dp_mst_get_modes(struct drm_connector *connector) 215 { 216 return radeon_dp_mst_get_ddc_modes(connector); 217 } 218 219 static enum drm_mode_status 220 radeon_dp_mst_mode_valid(struct drm_connector *connector, 221 struct drm_display_mode *mode) 222 { 223 /* TODO - validate mode against available PBN for link */ 224 if (mode->clock < 10000) 225 return MODE_CLOCK_LOW; 226 227 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 228 return MODE_H_ILLEGAL; 229 230 return MODE_OK; 231 } 232 233 static struct 234 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector) 235 { 236 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 237 238 return &radeon_connector->mst_encoder->base; 239 } 240 241 static int 242 radeon_dp_mst_detect(struct drm_connector *connector, 243 struct drm_modeset_acquire_ctx *ctx, 244 bool force) 245 { 246 struct radeon_connector *radeon_connector = 247 to_radeon_connector(connector); 248 struct radeon_connector *master = radeon_connector->mst_port; 249 250 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 251 radeon_connector->port); 252 } 253 254 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = { 255 .get_modes = radeon_dp_mst_get_modes, 256 .mode_valid = radeon_dp_mst_mode_valid, 257 .best_encoder = radeon_mst_best_encoder, 258 .detect_ctx = radeon_dp_mst_detect, 259 }; 260 261 static void 262 radeon_dp_mst_connector_destroy(struct drm_connector *connector) 263 { 264 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 265 struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder; 266 267 drm_encoder_cleanup(&radeon_encoder->base); 268 kfree(radeon_encoder); 269 drm_connector_cleanup(connector); 270 kfree(radeon_connector); 271 } 272 273 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = { 274 .dpms = drm_helper_connector_dpms, 275 .fill_modes = drm_helper_probe_single_connector_modes, 276 .destroy = radeon_dp_mst_connector_destroy, 277 }; 278 279 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 280 struct drm_dp_mst_port *port, 281 const char *pathprop) 282 { 283 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); 284 struct drm_device *dev = master->base.dev; 285 struct radeon_connector *radeon_connector; 286 struct drm_connector *connector; 287 288 radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL); 289 if (!radeon_connector) 290 return NULL; 291 292 radeon_connector->is_mst_connector = true; 293 connector = &radeon_connector->base; 294 radeon_connector->port = port; 295 radeon_connector->mst_port = master; 296 DRM_DEBUG_KMS("\n"); 297 298 drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); 299 drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs); 300 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master); 301 302 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); 303 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); 304 drm_connector_set_path_property(connector, pathprop); 305 306 return connector; 307 } 308 309 static void radeon_dp_register_mst_connector(struct drm_connector *connector) 310 { 311 struct drm_device *dev = connector->dev; 312 struct radeon_device *rdev = dev->dev_private; 313 314 radeon_fb_add_connector(rdev, connector); 315 316 drm_connector_register(connector); 317 } 318 319 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 320 struct drm_connector *connector) 321 { 322 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); 323 struct drm_device *dev = master->base.dev; 324 struct radeon_device *rdev = dev->dev_private; 325 326 drm_connector_unregister(connector); 327 radeon_fb_remove_connector(rdev, connector); 328 drm_connector_cleanup(connector); 329 330 kfree(connector); 331 DRM_DEBUG_KMS("\n"); 332 } 333 334 static const struct drm_dp_mst_topology_cbs mst_cbs = { 335 .add_connector = radeon_dp_add_mst_connector, 336 .register_connector = radeon_dp_register_mst_connector, 337 .destroy_connector = radeon_dp_destroy_mst_connector, 338 }; 339 340 static struct 341 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder) 342 { 343 struct drm_device *dev = encoder->dev; 344 struct drm_connector *connector; 345 346 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 347 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 348 if (!connector->encoder) 349 continue; 350 if (!radeon_connector->is_mst_connector) 351 continue; 352 353 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder); 354 if (connector->encoder == encoder) 355 return radeon_connector; 356 } 357 return NULL; 358 } 359 360 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 361 { 362 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 363 struct drm_device *dev = crtc->dev; 364 struct radeon_device *rdev = dev->dev_private; 365 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); 366 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; 367 struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base); 368 int dp_clock; 369 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; 370 371 if (radeon_connector) { 372 radeon_connector->pixelclock_for_modeset = mode->clock; 373 if (radeon_connector->base.display_info.bpc) 374 radeon_crtc->bpc = radeon_connector->base.display_info.bpc; 375 else 376 radeon_crtc->bpc = 8; 377 } 378 379 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock); 380 dp_clock = dig_connector->dp_clock; 381 radeon_crtc->ss_enabled = 382 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 383 ASIC_INTERNAL_SS_ON_DP, 384 dp_clock); 385 } 386 387 static void 388 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) 389 { 390 struct drm_device *dev = encoder->dev; 391 struct radeon_device *rdev = dev->dev_private; 392 struct radeon_encoder *radeon_encoder, *primary; 393 struct radeon_encoder_mst *mst_enc; 394 struct radeon_encoder_atom_dig *dig_enc; 395 struct radeon_connector *radeon_connector; 396 struct drm_crtc *crtc; 397 struct radeon_crtc *radeon_crtc; 398 int ret __unused, slots; 399 s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp; 400 if (!ASIC_IS_DCE5(rdev)) { 401 DRM_ERROR("got mst dpms on non-DCE5\n"); 402 return; 403 } 404 405 radeon_connector = radeon_mst_find_connector(encoder); 406 if (!radeon_connector) 407 return; 408 409 radeon_encoder = to_radeon_encoder(encoder); 410 411 mst_enc = radeon_encoder->enc_priv; 412 413 primary = mst_enc->primary; 414 415 dig_enc = primary->enc_priv; 416 417 crtc = encoder->crtc; 418 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links); 419 420 switch (mode) { 421 case DRM_MODE_DPMS_ON: 422 dig_enc->active_mst_links++; 423 424 radeon_crtc = to_radeon_crtc(crtc); 425 426 if (dig_enc->active_mst_links == 1) { 427 mst_enc->fe = dig_enc->dig_encoder; 428 mst_enc->fe_from_be = true; 429 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); 430 431 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0); 432 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, 433 0, 0, dig_enc->dig_encoder); 434 435 if (radeon_dp_needs_link_train(mst_enc->connector) || 436 dig_enc->active_mst_links == 1) { 437 radeon_dp_link_train(&primary->base, &mst_enc->connector->base); 438 } 439 440 } else { 441 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); 442 if (mst_enc->fe == -1) 443 DRM_ERROR("failed to get frontend for dig encoder\n"); 444 mst_enc->fe_from_be = false; 445 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); 446 } 447 448 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder, 449 dig_enc->linkb, radeon_crtc->crtc_id); 450 451 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr, 452 mst_enc->pbn); 453 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr, 454 radeon_connector->port, 455 mst_enc->pbn, slots); 456 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); 457 458 radeon_dp_mst_set_be_cntl(primary, mst_enc, 459 radeon_connector->mst_port->hpd.hpd, true); 460 461 mst_enc->enc_active = true; 462 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); 463 464 fixed_pbn = drm_int2fixp(mst_enc->pbn); 465 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div); 466 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot); 467 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp); 468 469 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, 470 mst_enc->fe); 471 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); 472 473 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); 474 475 break; 476 case DRM_MODE_DPMS_STANDBY: 477 case DRM_MODE_DPMS_SUSPEND: 478 case DRM_MODE_DPMS_OFF: 479 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links); 480 481 if (!mst_enc->enc_active) 482 return; 483 484 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port); 485 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); 486 487 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); 488 /* and this can also fail */ 489 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); 490 491 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port); 492 493 mst_enc->enc_active = false; 494 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); 495 496 radeon_dp_mst_set_be_cntl(primary, mst_enc, 497 radeon_connector->mst_port->hpd.hpd, false); 498 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, 499 mst_enc->fe); 500 501 if (!mst_enc->fe_from_be) 502 radeon_atom_release_dig_encoder(rdev, mst_enc->fe); 503 504 mst_enc->fe_from_be = false; 505 dig_enc->active_mst_links--; 506 if (dig_enc->active_mst_links == 0) { 507 /* drop link */ 508 } 509 510 break; 511 } 512 513 } 514 515 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder, 516 const struct drm_display_mode *mode, 517 struct drm_display_mode *adjusted_mode) 518 { 519 struct radeon_encoder_mst *mst_enc; 520 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 521 struct radeon_connector_atom_dig *dig_connector; 522 int bpp = 24; 523 524 mst_enc = radeon_encoder->enc_priv; 525 526 mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false); 527 528 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices; 529 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", 530 mst_enc->primary->active_device, mst_enc->primary->devices, 531 mst_enc->connector->devices, mst_enc->primary->base.encoder_type); 532 533 534 drm_mode_set_crtcinfo(adjusted_mode, 0); 535 dig_connector = mst_enc->connector->con_priv; 536 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); 537 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); 538 DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, 539 dig_connector->dp_lane_count, dig_connector->dp_clock); 540 return true; 541 } 542 543 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder) 544 { 545 struct radeon_connector *radeon_connector; 546 struct radeon_encoder *radeon_encoder, *primary; 547 struct radeon_encoder_mst *mst_enc; 548 struct radeon_encoder_atom_dig *dig_enc; 549 550 radeon_connector = radeon_mst_find_connector(encoder); 551 if (!radeon_connector) { 552 DRM_DEBUG_KMS("failed to find connector %p\n", encoder); 553 return; 554 } 555 radeon_encoder = to_radeon_encoder(encoder); 556 557 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 558 559 mst_enc = radeon_encoder->enc_priv; 560 561 primary = mst_enc->primary; 562 563 dig_enc = primary->enc_priv; 564 565 mst_enc->port = radeon_connector->port; 566 567 if (dig_enc->dig_encoder == -1) { 568 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); 569 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder); 570 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder); 571 572 573 } 574 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset); 575 } 576 577 static void 578 radeon_mst_encoder_mode_set(struct drm_encoder *encoder, 579 struct drm_display_mode *mode, 580 struct drm_display_mode *adjusted_mode) 581 { 582 DRM_DEBUG_KMS("\n"); 583 } 584 585 static void radeon_mst_encoder_commit(struct drm_encoder *encoder) 586 { 587 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 588 DRM_DEBUG_KMS("\n"); 589 } 590 591 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = { 592 .dpms = radeon_mst_encoder_dpms, 593 .mode_fixup = radeon_mst_mode_fixup, 594 .prepare = radeon_mst_encoder_prepare, 595 .mode_set = radeon_mst_encoder_mode_set, 596 .commit = radeon_mst_encoder_commit, 597 }; 598 599 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder) 600 { 601 drm_encoder_cleanup(encoder); 602 kfree(encoder); 603 } 604 605 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = { 606 .destroy = radeon_dp_mst_encoder_destroy, 607 }; 608 609 static struct radeon_encoder * 610 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector) 611 { 612 struct drm_device *dev = connector->base.dev; 613 struct radeon_device *rdev = dev->dev_private; 614 struct radeon_encoder *radeon_encoder; 615 struct radeon_encoder_mst *mst_enc; 616 struct drm_encoder *encoder; 617 const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private; 618 struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base); 619 620 DRM_DEBUG_KMS("enc master is %p\n", enc_master); 621 radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL); 622 if (!radeon_encoder) 623 return NULL; 624 625 radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL); 626 if (!radeon_encoder->enc_priv) { 627 kfree(radeon_encoder); 628 return NULL; 629 } 630 encoder = &radeon_encoder->base; 631 switch (rdev->num_crtc) { 632 case 1: 633 encoder->possible_crtcs = 0x1; 634 break; 635 case 2: 636 default: 637 encoder->possible_crtcs = 0x3; 638 break; 639 case 4: 640 encoder->possible_crtcs = 0xf; 641 break; 642 case 6: 643 encoder->possible_crtcs = 0x3f; 644 break; 645 } 646 647 drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs, 648 DRM_MODE_ENCODER_DPMST, NULL); 649 drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs); 650 651 mst_enc = radeon_encoder->enc_priv; 652 mst_enc->connector = connector; 653 mst_enc->primary = to_radeon_encoder(enc_master); 654 radeon_encoder->is_mst_encoder = true; 655 return radeon_encoder; 656 } 657 658 int 659 radeon_dp_mst_init(struct radeon_connector *radeon_connector) 660 { 661 struct drm_device *dev = radeon_connector->base.dev; 662 663 if (!radeon_connector->ddc_bus->has_aux) 664 return 0; 665 666 radeon_connector->mst_mgr.cbs = &mst_cbs; 667 return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, 668 &radeon_connector->ddc_bus->aux, 16, 6, 669 radeon_connector->base.base.id); 670 } 671 672 int 673 radeon_dp_mst_probe(struct radeon_connector *radeon_connector) 674 { 675 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 676 struct drm_device *dev = radeon_connector->base.dev; 677 struct radeon_device *rdev = dev->dev_private; 678 int ret; 679 u8 msg[1]; 680 681 if (!radeon_mst) 682 return 0; 683 684 if (!ASIC_IS_DCE5(rdev)) 685 return 0; 686 687 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) 688 return 0; 689 690 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg, 691 1); 692 if (ret) { 693 if (msg[0] & DP_MST_CAP) { 694 DRM_DEBUG_KMS("Sink is MST capable\n"); 695 dig_connector->is_mst = true; 696 } else { 697 DRM_DEBUG_KMS("Sink is not MST capable\n"); 698 dig_connector->is_mst = false; 699 } 700 701 } 702 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, 703 dig_connector->is_mst); 704 return dig_connector->is_mst; 705 } 706 707 int 708 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector) 709 { 710 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 711 int retry; 712 713 if (dig_connector->is_mst) { 714 u8 esi[16] = { 0 }; 715 int dret; 716 int ret = 0; 717 bool handled; 718 719 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, 720 DP_SINK_COUNT_ESI, esi, 8); 721 go_again: 722 if (dret == 8) { 723 DRM_DEBUG_KMS("got esi %3ph\n", esi); 724 ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled); 725 726 if (handled) { 727 for (retry = 0; retry < 3; retry++) { 728 int wret; 729 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, 730 DP_SINK_COUNT_ESI + 1, &esi[1], 3); 731 if (wret == 3) 732 break; 733 } 734 735 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, 736 DP_SINK_COUNT_ESI, esi, 8); 737 if (dret == 8) { 738 DRM_DEBUG_KMS("got esi2 %3ph\n", esi); 739 goto go_again; 740 } 741 } else 742 ret = 0; 743 744 return ret; 745 } else { 746 DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret); 747 dig_connector->is_mst = false; 748 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, 749 dig_connector->is_mst); 750 /* send a hotplug event */ 751 } 752 } 753 return -EINVAL; 754 } 755 756 #if defined(CONFIG_DEBUG_FS) 757 758 static int radeon_debugfs_mst_info(struct seq_file *m, void *data) 759 { 760 struct drm_info_node *node = (struct drm_info_node *)m->private; 761 struct drm_device *dev = node->minor->dev; 762 struct drm_connector *connector; 763 struct radeon_connector *radeon_connector; 764 struct radeon_connector_atom_dig *dig_connector; 765 int i; 766 767 drm_modeset_lock_all(dev); 768 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 769 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 770 continue; 771 772 radeon_connector = to_radeon_connector(connector); 773 dig_connector = radeon_connector->con_priv; 774 if (radeon_connector->is_mst_connector) 775 continue; 776 if (!dig_connector->is_mst) 777 continue; 778 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr); 779 780 for (i = 0; i < radeon_connector->enabled_attribs; i++) 781 seq_printf(m, "attrib %d: %d %d\n", i, 782 radeon_connector->cur_stream_attribs[i].fe, 783 radeon_connector->cur_stream_attribs[i].slots); 784 } 785 drm_modeset_unlock_all(dev); 786 return 0; 787 } 788 789 static struct drm_info_list radeon_debugfs_mst_list[] = { 790 {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL}, 791 }; 792 #endif 793 794 int radeon_mst_debugfs_init(struct radeon_device *rdev) 795 { 796 #if defined(CONFIG_DEBUG_FS) 797 return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1); 798 #endif 799 return 0; 800 } 801
Indexes created Sat Sep 20 22:09:52 GMT 2025