HomeSort by: relevance | last modified time | path
    Searched refs:radeon_get_ib_value (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600_cs.c 854 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
870 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
875 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
889 header = radeon_get_ib_value(p, h_idx);
890 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1011 /*tmp =radeon_get_ib_value(p, idx);
1029 track->sq_config = radeon_get_ib_value(p, idx);
1032 track->db_depth_control = radeon_get_ib_value(p, idx);
1044 track->db_depth_info = radeon_get_ib_value(p, idx);
1055 track->db_depth_info = radeon_get_ib_value(p, idx)
    [all...]
radeon_evergreen_cs.c 793 texdw[0] = radeon_get_ib_value(p, idx + 0);
794 texdw[1] = radeon_get_ib_value(p, idx + 1);
795 texdw[2] = radeon_get_ib_value(p, idx + 2);
796 texdw[3] = radeon_get_ib_value(p, idx + 3);
797 texdw[4] = radeon_get_ib_value(p, idx + 4);
798 texdw[5] = radeon_get_ib_value(p, idx + 5);
799 texdw[6] = radeon_get_ib_value(p, idx + 6);
800 texdw[7] = radeon_get_ib_value(p, idx + 7);
1161 /*tmp =radeon_get_ib_value(p, idx);
1181 track->db_depth_control = radeon_get_ib_value(p, idx)
    [all...]
radeon_vce.c 536 offset = radeon_get_ib_value(p, lo);
537 idx = radeon_get_ib_value(p, hi);
623 uint32_t len = radeon_get_ib_value(p, p->idx);
624 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
640 handle = radeon_get_ib_value(p, p->idx + 2);
659 *size = radeon_get_ib_value(p, p->idx + 8) *
660 radeon_get_ib_value(p, p->idx + 10) *
696 tmp = radeon_get_ib_value(p, p->idx + 4);
radeon_r300.c 674 idx_value = radeon_get_ib_value(p, idx);
1230 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1241 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1245 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1256 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1260 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1268 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1275 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1282 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1289 track->vap_vf_cntl = radeon_get_ib_value(p, idx)
    [all...]
radeon_r100.c 1297 value = radeon_get_ib_value(p, idx);
1333 c = radeon_get_ib_value(p, idx++) & 0x1F;
1349 idx_value = radeon_get_ib_value(p, idx);
1350 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1362 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1375 idx_value = radeon_get_ib_value(p, idx);
1376 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1467 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1481 header = radeon_get_ib_value(p, h_idx);
1482 crtc_id = radeon_get_ib_value(p, h_idx + 5)
    [all...]
radeon_cs.c 761 header = radeon_get_ib_value(p, idx);
797 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
799 printk("\t0x%08x\n", radeon_get_ib_value(p, i));
882 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
radeon_uvd.c 590 offset = radeon_get_ib_value(p, data0);
591 idx = radeon_get_ib_value(p, data1);
606 cmd = radeon_get_ib_value(p, p->idx) >> 1;
radeon_r200.c 166 idx_value = radeon_get_ib_value(p, idx);
radeon.h 1136 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) function

Completed in 46 milliseconds