| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_uvd_v3_1.c | 51 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
52 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
54 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
55 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
57 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
58 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
|
| radeon_evergreen_dma.c | 52 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
53 radeon_ring_write(ring, addr & 0xfffffffc);
54 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
55 radeon_ring_write(ring, fence->seq);
57 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
59 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
60 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
61 radeon_ring_write(ring, 1);
82 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
83 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc)
[all...] |
| radeon_uvd_v2_2.c | 50 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
51 radeon_ring_write(ring, fence->seq);
52 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
53 radeon_ring_write(ring, lower_32_bits(addr));
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
55 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
57 radeon_ring_write(ring, 0);
59 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
60 radeon_ring_write(ring, 0)
[all...] |
| radeon_uvd_v1_0.c | 92 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
93 radeon_ring_write(ring, addr & 0xffffffff);
94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
95 radeon_ring_write(ring, fence->seq);
96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
97 radeon_ring_write(ring, 0);
99 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
100 radeon_ring_write(ring, 0);
101 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
102 radeon_ring_write(ring, 0)
[all...] |
| radeon_si_dma.c | 196 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
198 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));
200 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2));
202 radeon_ring_write(ring, pd_addr >> 12);
205 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
206 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
207 radeon_ring_write(ring, 1);
210 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
211 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
212 radeon_ring_write(ring, 1 << vm_id)
[all...] |
| radeon_cik_sdma.c | 149 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
150 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
151 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
152 radeon_ring_write(ring, 1); /* number of DWs to follow */
153 radeon_ring_write(ring, next_rptr);
158 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
159 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
160 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
161 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
162 radeon_ring_write(ring, ib->length_dw)
[all...] |
| radeon_ni_dma.c | 138 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
139 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
140 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
141 radeon_ring_write(ring, next_rptr);
148 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
149 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0));
150 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
151 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
457 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
458 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2))
[all...] |
| radeon_rv770_dma.c | 79 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
80 radeon_ring_write(ring, dst_offset & 0xfffffffc);
81 radeon_ring_write(ring, src_offset & 0xfffffffc);
82 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
83 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
|
| radeon_r600_dma.c | 258 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
259 radeon_ring_write(ring, lower_32_bits(gpu_addr));
260 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
261 radeon_ring_write(ring, 0xDEADBEEF);
298 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
299 radeon_ring_write(ring, addr & 0xfffffffc);
300 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
301 radeon_ring_write(ring, lower_32_bits(fence->seq));
303 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
325 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0))
[all...] |
| radeon_r300.c | 251 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
252 radeon_ring_write(ring, 0);
253 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
254 radeon_ring_write(ring, 0);
256 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
257 radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
258 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
259 radeon_ring_write(ring, R300_ZC_FLUSH);
261 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
262 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN
[all...] |
| radeon_ni.c | 1418 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1419 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1420 radeon_ring_write(ring, 0xFFFFFFFF);
1421 radeon_ring_write(ring, 0);
1422 radeon_ring_write(ring, 10); /* poll interval */
1424 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1425 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1426 radeon_ring_write(ring, lower_32_bits(addr));
1427 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1428 radeon_ring_write(ring, fence->seq)
[all...] |
| radeon_rv515.c | 80 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
81 radeon_ring_write(ring,
86 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
87 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
89 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
90 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
91 radeon_ring_write(ring, 0);
92 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
93 radeon_ring_write(ring, 0)
[all...] |
| radeon_r200.c | 110 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
111 radeon_ring_write(ring, (1 << 16));
118 radeon_ring_write(ring, PACKET0(0x720, 2));
119 radeon_ring_write(ring, src_offset);
120 radeon_ring_write(ring, dst_offset);
121 radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));
125 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
126 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
|
| radeon_vce.c | 759 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE));
760 radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF));
761 radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF));
762 radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));
764 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
779 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB));
780 radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr));
781 radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));
782 radeon_ring_write(ring, cpu_to_le32(ib->length_dw));
798 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE))
[all...] |
| radeon_r600.c | 2729 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2730 radeon_ring_write(ring, 0x1);
2732 radeon_ring_write(ring, 0x0);
2733 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2735 radeon_ring_write(ring, 0x3);
2736 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2738 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2739 radeon_ring_write(ring, 0);
2740 radeon_ring_write(ring, 0);
2874 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1))
[all...] |
| radeon_si.c | 3388 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3389 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3390 radeon_ring_write(ring, 0);
3391 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3392 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3396 radeon_ring_write(ring, 0xFFFFFFFF);
3397 radeon_ring_write(ring, 0);
3398 radeon_ring_write(ring, 10); /* poll interval */
3400 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3401 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5))
[all...] |
| radeon_r420.c | 230 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
231 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
232 radeon_ring_write(ring, 0xDEADBEEF);
246 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
247 radeon_ring_write(ring, R300_RB3D_DC_FINISH);
|
| radeon_cik.c | 3491 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3492 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3493 radeon_ring_write(ring, 0xDEADBEEF);
3547 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3548 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3551 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3552 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3553 radeon_ring_write(ring, ref_and_mask);
3554 radeon_ring_write(ring, ref_and_mask);
3555 radeon_ring_write(ring, 0x20); /* poll interval *
[all...] |
| radeon_r100.c | 868 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
869 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
871 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
872 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
884 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
885 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
886 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
887 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
889 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
890 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN)
[all...] |
| radeon_evergreen.c | 2941 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
2942 radeon_ring_write(ring, 1);
2946 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2947 radeon_ring_write(ring, ((ring->rptr_save_reg -
2949 radeon_ring_write(ring, next_rptr);
2952 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2953 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2954 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
2955 radeon_ring_write(ring, next_rptr);
2956 radeon_ring_write(ring, 0)
[all...] |
| radeon_ring.c | 183 radeon_ring_write(ring, ring->nop);
364 radeon_ring_write(ring, data[i]);
|
| radeon.h | 2757 * radeon_ring_write - write a value to the ring
2764 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) function in typeref:typename:void
|
