| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/ |
| nouveau_nvkm_engine_fifo_dmag84.c | 72 nvkm_kmap(chan->ramfc);
73 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
74 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
75 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
76 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
77 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
81 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff)
[all...] |
| nouveau_nvkm_engine_fifo_dmanv50.c | 72 nvkm_kmap(chan->ramfc);
73 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
74 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
75 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
76 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
77 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
81 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff)
[all...] |
| nouveau_nvkm_engine_fifo_gpfifog84.c | 76 nvkm_kmap(chan->ramfc);
77 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset));
81 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
82 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
83 nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
84 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
85 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27)
[all...] |
| nouveau_nvkm_engine_fifo_dmanv10.c | 79 chan->ramfc = chan->base.chid * 32;
81 nvkm_kmap(imem->ramfc);
82 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
83 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
84 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);
85 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14
[all...] |
| nouveau_nvkm_engine_fifo_dmanv17.c | 80 chan->ramfc = chan->base.chid * 64;
82 nvkm_kmap(imem->ramfc);
83 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
84 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
85 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);
86 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14
[all...] |
| nouveau_nvkm_engine_fifo_gpfifonv50.c | 76 nvkm_kmap(chan->ramfc);
77 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset));
81 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
82 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
83 nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
84 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
85 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27)
[all...] |
| nouveau_nvkm_engine_fifo_dmanv40.c | 84 nvkm_kmap(imem->ramfc);
85 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000);
86 nvkm_done(imem->ramfc);
115 nvkm_kmap(imem->ramfc);
116 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst);
117 nvkm_done(imem->ramfc);
227 chan->ramfc = chan->base.chid * 128;
229 nvkm_kmap(imem->ramfc);
[all...] |
| nv04.h | 19 const struct nv04_fifo_ramfc *ramfc; member in struct:nv04_fifo
|
| nouveau_nvkm_engine_fifo_dmanv04.c | 84 struct nvkm_memory *fctx = device->imem->ramfc;
88 u32 data = chan->ramfc;
102 c = fifo->ramfc;
113 c = fifo->ramfc;
150 const struct nv04_fifo_ramfc *c = fifo->ramfc;
152 nvkm_kmap(imem->ramfc);
154 nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000);
156 nvkm_done(imem->ramfc);
208 chan->ramfc = chan->base.chid * 32
[all...] |
| channv04.h | 13 u32 ramfc; member in struct:nv04_fifo_chan
|
| nouveau_nvkm_engine_fifo_nv17.c | 63 struct nvkm_memory *ramfc = imem->ramfc; local in function:nv17_fifo_init
72 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 |
|
| nouveau_nvkm_engine_fifo_nv40.c | 73 struct nvkm_memory *ramfc = imem->ramfc; local in function:nv40_fifo_init
101 nvkm_memory_addr(ramfc)) >> 16) |
|
| channv50.h | 14 struct nvkm_gpuobj *ramfc; member in struct:nv50_fifo_chan
|
| nouveau_nvkm_engine_fifo_nv04.c | 311 struct nvkm_memory *ramfc = imem->ramfc; local in function:nv04_fifo_init
320 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8);
334 int index, int nr, const struct nv04_fifo_ramfc *ramfc,
342 fifo->ramfc = ramfc;
|
| nouveau_nvkm_engine_fifo_channv50.c | 203 u64 addr = chan->ramfc->addr >> 12;
218 nvkm_gpuobj_del(&chan->ramfc);
258 &chan->ramfc);
|
| nouveau_nvkm_engine_fifo_chang84.c | 215 u64 addr = chan->ramfc->addr >> 8;
284 &chan->ramfc);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| instmem.h | 21 struct nvkm_memory *ramfc; member in struct:nvkm_instmem
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/instmem/ |
| nouveau_nvkm_subdev_instmem_nv04.c | 193 /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
195 &imem->base.ramfc);
212 nvkm_memory_unref(&imem->base.ramfc);
|
| nouveau_nvkm_subdev_instmem_nv40.c | 237 /* 0x20000-0x21000: reserve for RAMFC
241 &imem->base.ramfc);
252 nvkm_memory_unref(&imem->base.ramfc);
|
