| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| dscc_types.h | 40 int range_bpg_offset; member in struct:dsc_pps_rc_range
|
| amdgpu_rc_calc_dpi.c | 95 dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dsc.c | 329 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
667 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
672 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
675 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
680 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
683 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
688 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
691 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
696 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
[all...] |
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dsc.h | 65 * @range_bpg_offset:
68 u8 range_bpg_offset; member in struct:drm_dsc_rc_range_parameters
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dsc.c | 229 (dsc_cfg->rc_range_params[i].range_bpg_offset));
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_vdsc.c | 448 vdsc_cfg->rc_range_params[i].range_bpg_offset =
449 rc_params->rc_range_params[i].range_bpg_offset &
817 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
|
