| /src/sys/stand/ |
| copy.c | 54 register int from, to, record, rcc, wcc, bsize = BSIZE; local in function:main
60 if (!(rcc = read(from, buf, bsize)))
62 if (rcc < 0) {
67 if (rcc != bsize) {
69 bsize = rcc;
74 record, bsize, rcc);
78 if (rcc > bsize)
79 rcc = bsize;
81 if ((wcc = write(to, buf, rcc)) < 0) {
86 if (wcc < rcc) {
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| stm32f469.dtsi | 11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
13 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
|
| stm32f746.dtsi | 45 #include <dt-bindings/mfd/stm32f7-rcc.h>
82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>
569 rcc: rcc@40023800 { label
[all...] |
| stm32mp157.dtsi | 15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
25 resets = <&rcc DSI_R>;
|
| stm32f429.dtsi | 50 #include <dt-bindings/mfd/stm32f4-rcc.h>
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>
704 rcc: rcc@40023800 { label
[all...] |
| stm32h743.dtsi | 45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>
537 rcc: reset-clock-controller@58024400 { label
[all...] |
| stm32mp151.dtsi | 130 clocks = <&rcc TIM2_K>;
163 clocks = <&rcc TIM3_K>;
197 clocks = <&rcc TIM4_K>;
229 clocks = <&rcc TIM5_K>;
263 clocks = <&rcc TIM6_K>;
281 clocks = <&rcc TIM7_K>;
299 clocks = <&rcc TIM12_K>;
321 clocks = <&rcc TIM13_K>;
343 clocks = <&rcc TIM14_K>;
366 clocks = <&rcc LPTIM1_K>
1119 rcc: rcc@50000000 { label
[all...] |
| stm32mp15xc.dtsi | 13 clocks = <&rcc CRYP1>;
14 resets = <&rcc CRYP1_R>;
|
| stm32mp153.dtsi | 33 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
46 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
| stm32f7-pinctrl.dtsi | 8 #include <dt-bindings/mfd/stm32f7-rcc.h>
26 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
36 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
46 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
56 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
66 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
76 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
86 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
96 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
106 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>
[all...] |
| stm32f4-pinctrl.dtsi | 44 #include <dt-bindings/mfd/stm32f4-rcc.h>
62 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
72 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
82 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
92 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
102 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
112 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
122 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
132 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
142 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>
[all...] |
| stm32f769-disco.dts | 91 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
103 &rcc {
104 compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
|
| stm32mp157c-odyssey.dts | 33 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
34 assigned-clock-parents = <&rcc PLL4_P>;
|
| stm32f429-disco.dts | 169 assigned-clocks = <&rcc 1 CLK_RTC>;
170 assigned-clock-parents = <&rcc 1 CLK_LSI>;
|
| stm32f746-disco.dts | 70 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
|
| stm32mp15xx-dhcom-pdk2.dtsi | 228 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
238 clocks = <&rcc SAI2_K>;
256 clocks = <&rcc SAI2_K>, <&sai2a>;
|
| stm32h743i-eval.dts | 84 clocks = <&rcc USB1ULPI_CK>;
|
| stm32mp15xx-dkx.dtsi | 431 clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
494 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
504 clocks = <&rcc SAI2_K>;
522 clocks = <&rcc SAI2_K>, <&sai2a>;
|
| stm32f469-disco.dts | 127 &rcc {
128 compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
|
| stm32mp15xx-dhcor-avenger96.dtsi | 289 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
299 clocks = <&rcc SAI2_K>;
|
| stm32746g-eval.dts | 133 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
|
| stm32429i-eval.dts | 140 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
|
| stm32mp15xx-dhcom-som.dtsi | 139 clocks = <&rcc ETHCK_K>;
|
| /src/lib/libc/citrus/ |
| citrus_ctype.c | 142 _citrus_ctype_open(_citrus_ctype_t *rcc,
152 _DIAGASSERT(rcc != NULL);
155 *rcc = &_citrus_ctype_default;
175 *rcc = cc;
199 _citrus_ctype_open(_citrus_ctype_t *rcc,
204 *rcc = &_citrus_ctype_default;
|
| /src/sys/kern/ |
| kern_cctr.c | 187 int64_t rcc; local in function:cc_get_timecount
193 rcc = cpu_counter32() - curcpu()->ci_cc.cc_delta;
196 return rcc;
|
