| /src/sys/dev/usb/ |
| if_url.c | 425 uint32_t h = 0, rcr; local in function:url_uno_mcast
432 rcr = url_csr_read_2(un, URL_RCR);
433 rcr &= ~(URL_RCR_AAP | URL_RCR_AAM | URL_RCR_AM);
440 rcr |= URL_RCR_AAM; /* ??? */
441 rcr |= URL_RCR_AAP;
451 rcr |= URL_RCR_AAM;
461 rcr |= URL_RCR_AM; /* activate mcast hash filter */
465 url_csr_write_2(un, URL_RCR, rcr);
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| /src/sys/arch/amiga/dev/ |
| if_esreg.h | 36 volatile u_short rcr; /* Receive Control Register */ member in struct:smcregs::__anonf052b2be0108
|
| if_es.c | 209 printf("TCR %04x EPHSR %04x RCR %04x ECR %04x MIR %04x MCR %04x\n",
210 SWAP(smc->b0.tcr), SWAP(smc->b0.ephsr), SWAP(smc->b0.rcr),
244 smc->b0.rcr = 0;
267 smc->b0.rcr = RCR_EPH_RST;
268 smc->b0.rcr = 0;
286 smc->b0.rcr = RCR_FILT_CAR | RCR_STRIP_CRC | RCR_RXEN | RCR_ALLMUL;
|
| /src/sys/external/bsd/acpica/dist/include/platform/ |
| acmsvc.h | 254 __asm rcr n_lo, 1 \
|
| /src/sys/dev/ic/ |
| dm9000.c | 405 int rcr; local in function:dme_set_rcvfilt
407 rcr = dme_read(sc, DM9000_RCR);
408 rcr &= ~(DM9000_RCR_PRMSC | DM9000_RCR_ALL);
409 dme_write(sc, DM9000_RCR, rcr &~ DM9000_RCR_RXEN);
416 rcr |= DM9000_RCR_PRMSC;
435 rcr |= DM9000_RCR_ALL;
448 dme_write(sc, DM9000_RCR, rcr | DM9000_RCR_RXEN);
|
| dp83932.c | 1188 uint16_t rcr = 0; local in function:sonic_set_filter
1191 rcr |= RCR_BRD;
1194 rcr |= RCR_PRO;
1241 rcr |= RCR_AMC;
1274 CSR_WRITE(sc, SONIC_RCR, rcr);
|
| rtw.c | 812 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr)
816 *rcr |= RTW_RCR_ENCS1;
822 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale,
831 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2);
840 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr);
868 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),
4029 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */
|
| /src/sys/arch/sandpoint/stand/altboot/ |
| rge.c | 124 unsigned tcr, rcr; member in struct:local
217 l->rcr = (07 << 13) | (07 << 8) | RCR_APM;
222 CSR_WRITE_4(l, RGE_RCR, l->rcr);
|
| /src/sys/arch/arm/imx/ |
| if_enet.c | 1120 uint32_t rcr, rcr0; local in function:enet_miibus_statchg
1129 rcr0 = rcr = ENET_REG_READ(sc, ENET_RCR);
1140 rcr &= ~ENET_RCR_DRT; /* enable receive on transmit */
1143 rcr |= ENET_RCR_DRT; /* disable receive on transmit */
1159 rcr &= ~ENET_RCR_RMII_10T;
1163 rcr &= ~ENET_RCR_RMII_10T; /* 100Mbps mode */
1167 rcr |= ENET_RCR_RMII_10T; /* 10Mbps mode */
1171 rcr = rcr0;
1180 rcr |= ENET_RCR_FCE;
1182 rcr &= ~ENET_RCR_FCE
[all...] |
| /src/sys/arch/x86/include/ |
| cpufunc.h | 224 static inline register_t rcr##crnum(void) \
237 register_t rcr##crnum(void);
|
| /src/sys/arch/evbppc/virtex/dev/ |
| if_temac.c | 582 uint32_t rcr, tcr; local in function:temac_init
596 rcr = (gmi_read_4(TEMAC_GMI_RXCF1) | GMI_RX_ENABLE) &
598 gmi_write_4(TEMAC_GMI_RXCF1, rcr);
1252 uint32_t rcr, tcr; local in function:temac_reset
1259 rcr = gmi_read_4(TEMAC_GMI_RXCF1) & ~GMI_RX_ENABLE;
1260 gmi_write_4(TEMAC_GMI_RXCF1, rcr);
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