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    Searched refs:read_map (Results 1 - 25 of 87) sorted by relevancy

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  /src/external/gpl3/gdb.old/dist/sim/common/
sim-hrw.c 33 return sim_core_read_buffer (sd, NULL, read_map,
sim-basics.h 56 read_map = 0, enumerator in enum:__anon21938
65 access_read = 1 << read_map,
sim-syscall.c 43 return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
  /src/external/gpl3/gdb/dist/sim/common/
sim-hrw.c 33 return sim_core_read_buffer (sd, NULL, read_map,
sim-basics.h 56 read_map = 0, enumerator in enum:__anon1423
65 access_read = 1 << read_map,
sim-syscall.c 43 return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
  /src/external/gpl3/gdb.old/dist/sim/aarch64/
memory.c 51 sim_core_read_unaligned_##N (cpu, 0, read_map, address); \
66 sim_core_read_unaligned_##N (cpu, 0, read_map, address); \
83 a->v[0] = sim_core_read_unaligned_8 (cpu, 0, read_map, address);
84 a->v[1] = sim_core_read_unaligned_8 (cpu, 0, read_map, address + 8);
128 len = sim_core_read_buffer (CPU_STATE (cpu), cpu, read_map,
144 char *addr = sim_core_trans_addr (CPU_STATE (cpu), cpu, read_map, address);
  /src/external/gpl3/gdb/dist/sim/aarch64/
memory.c 51 sim_core_read_unaligned_##N (cpu, 0, read_map, address); \
66 sim_core_read_unaligned_##N (cpu, 0, read_map, address); \
83 a->v[0] = sim_core_read_unaligned_8 (cpu, 0, read_map, address);
84 a->v[1] = sim_core_read_unaligned_8 (cpu, 0, read_map, address + 8);
128 len = sim_core_read_buffer (CPU_STATE (cpu), cpu, read_map,
144 char *addr = sim_core_trans_addr (CPU_STATE (cpu), cpu, read_map, address);
  /src/external/gpl3/gdb/dist/sim/mips/
sim-main.c 94 unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
100 value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
103 value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
106 value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
109 value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
112 value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
115 value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
118 value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
121 value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
  /src/external/gpl3/gdb.old/dist/sim/mips/
sim-main.c 94 unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
100 value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
103 value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
106 value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
109 value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
112 value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
115 value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
118 value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
121 value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
  /src/external/gpl3/gdb.old/dist/sim/microblaze/
microblaze.h 55 #define MEM_RD_BYTE(X) sim_core_read_1 (cpu, 0, read_map, X)
56 #define MEM_RD_HALF(X) sim_core_read_2 (cpu, 0, read_map, X)
57 #define MEM_RD_WORD(X) sim_core_read_4 (cpu, 0, read_map, X)
  /src/external/gpl3/gdb/dist/sim/microblaze/
microblaze.h 55 #define MEM_RD_BYTE(X) sim_core_read_1 (cpu, 0, read_map, X)
56 #define MEM_RD_HALF(X) sim_core_read_2 (cpu, 0, read_map, X)
57 #define MEM_RD_WORD(X) sim_core_read_4 (cpu, 0, read_map, X)
  /src/external/gpl3/gdb.old/dist/sim/cris/
crisv10f.c 87 read_map, entryaddr_le,
  /src/external/gpl3/gdb/dist/sim/cris/
crisv10f.c 87 read_map, entryaddr_le,
  /src/external/gpl3/gdb/dist/sim/mn10300/
mn10300-sim.h 137 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
140 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
143 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
147 PC, read_map, (ADDR)))
  /src/external/gpl3/gdb.old/dist/sim/mn10300/
mn10300-sim.h 137 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
140 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
143 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
147 PC, read_map, (ADDR)))
  /src/external/gpl3/gdb.old/dist/sim/lm32/
sim-if.c 130 if (sim_core_read_buffer (sd, NULL, read_map, &c, LM32_DEVICE_ADDR, 1) == 0)
146 if (sim_core_read_buffer (sd, NULL, read_map, &c, STATE_START_ADDR (sd), 1)
  /src/external/gpl3/gdb/dist/sim/lm32/
sim-if.c 130 if (sim_core_read_buffer (sd, NULL, read_map, &c, LM32_DEVICE_ADDR, 1) == 0)
146 if (sim_core_read_buffer (sd, NULL, read_map, &c, STATE_START_ADDR (sd), 1)
  /src/external/gpl3/gdb.old/dist/sim/cr16/
cr16-sim.h 381 #define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data)
382 #define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr)
383 #define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
384 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
385 #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
  /src/external/gpl3/gdb/dist/sim/cr16/
cr16-sim.h 381 #define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data)
382 #define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr)
383 #define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
384 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
385 #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
  /src/external/gpl3/gdb.old/dist/sim/moxie/
interp.c 47 ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 24) \
48 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1) << 16) \
49 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+2) << 8) \
50 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+3)))
55 ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 8) \
56 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1))) << 16) >> 16)
183 return (sim_core_read_aligned_2 (scpu, cia, read_map, x));
193 return (sim_core_read_aligned_1 (scpu, cia, read_map, x));
203 return (sim_core_read_aligned_4 (scpu, cia, read_map, x));
258 inst = (sim_core_read_aligned_1 (scpu, cia, read_map, pc) << 8
    [all...]
  /src/external/gpl3/gdb/dist/sim/moxie/
interp.c 47 ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 24) \
48 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1) << 16) \
49 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+2) << 8) \
50 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+3)))
55 ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 8) \
56 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1))) << 16) >> 16)
183 return (sim_core_read_aligned_2 (scpu, cia, read_map, x));
193 return (sim_core_read_aligned_1 (scpu, cia, read_map, x));
203 return (sim_core_read_aligned_4 (scpu, cia, read_map, x));
258 inst = (sim_core_read_aligned_1 (scpu, cia, read_map, pc) << 8
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/example-synacor/
interp.c 149 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
  /src/external/gpl3/gdb.old/dist/sim/riscv/
interp.c 136 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
  /src/external/gpl3/gdb/dist/sim/example-synacor/
interp.c 149 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)

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