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  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
move.s 9 .macro move reg0:req, reg1:req, clobber:req
10 imm32 \reg0, 0x5555aaaa
13 \reg0 = \reg1;
14 CC = \reg0 == \clobber;
load.s 9 .macro load32 num:req, reg0:req, reg1:req
10 imm32 \reg0 \num
12 CC = \reg0 == \reg1
29 .macro load16z num:req reg0:req reg1:req
30 \reg0 = \num (Z);
32 CC = \reg0 == \reg1
48 .macro load16x num:req reg0:req reg1:req
49 \reg0 = \num (X);
51 CC = \reg0 == \reg1
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
move.s 9 .macro move reg0:req, reg1:req, clobber:req
10 imm32 \reg0, 0x5555aaaa
13 \reg0 = \reg1;
14 CC = \reg0 == \clobber;
load.s 9 .macro load32 num:req, reg0:req, reg1:req
10 imm32 \reg0 \num
12 CC = \reg0 == \reg1
29 .macro load16z num:req reg0:req reg1:req
30 \reg0 = \num (Z);
32 CC = \reg0 == \reg1
48 .macro load16x num:req reg0:req reg1:req
49 \reg0 = \num (X);
51 CC = \reg0 == \reg1
  /src/external/gpl3/gcc/dist/gcc/
auto-inc-dec.cc 308 /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or
309 "reg_res = reg0+c". */
318 rtx reg0; member in struct:inc_insn
343 REGNO (inc_insn.reg0), (int) inc_insn.reg1_val);
348 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1));
369 /* Parsed fields of a mem ref of the form "*(reg0+reg1)" or "*(reg0+c)". */
378 rtx reg0; member in struct:mem_insn
396 REGNO (mem_insn.reg0), (int) mem_insn.reg1_val);
400 REGNO (mem_insn.reg0), REGNO (mem_insn.reg1))
    [all...]
sched-deps.cc 4946 rtx reg0 = XEXP (x, 0);
4951 if (GET_CODE (reg0) == PLUS && CONST_INT_P (XEXP (reg0, 1)))
4953 mii->mem_constant = INTVAL (XEXP (reg0, 1));
4954 reg0 = XEXP (reg0, 0);
4956 if (GET_CODE (reg0) == PLUS)
4958 mii->mem_index = XEXP (reg0, 1);
4959 reg0 = XEXP (reg0, 0)
4936 rtx reg0 = XEXP (x, 0); local
    [all...]
  /src/external/gpl3/gcc.old/dist/gcc/
auto-inc-dec.cc 308 /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or
309 "reg_res = reg0+c". */
318 rtx reg0; member in struct:inc_insn
343 REGNO (inc_insn.reg0), (int) inc_insn.reg1_val);
348 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1));
369 /* Parsed fields of a mem ref of the form "*(reg0+reg1)" or "*(reg0+c)". */
378 rtx reg0; member in struct:mem_insn
396 REGNO (mem_insn.reg0), (int) mem_insn.reg1_val);
400 REGNO (mem_insn.reg0), REGNO (mem_insn.reg1))
    [all...]
  /src/sys/dev/ic/
rtwvar.h 118 * Complete outstanding read and/or write ops on [reg0, reg1]
119 * ([reg1, reg0]) before starting new ops on the same region. See
123 rtw_barrier(const struct rtw_regs *r, int reg0, int reg1, int flags)
125 bus_space_barrier(r->r_bt, r->r_bh, MIN(reg0, reg1),
126 MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags);
133 #define RTW_SYNC(regs, reg0, reg1) \
134 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
137 #define RTW_WBW(regs, reg0, reg1) \
138 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE
    [all...]
smc83c170.c 898 uint32_t genctl, reg0; local
931 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL);
932 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1);
938 bus_space_write_4(st, sh, EPIC_NVCTL, reg0);
943 reg0 = enaddr[1] << 8 | enaddr[0];
944 bus_space_write_4(st, sh, EPIC_LAN0, reg0);
945 reg0 = enaddr[3] << 8 | enaddr[2];
946 bus_space_write_4(st, sh, EPIC_LAN1, reg0);
947 reg0 = enaddr[5] << 8 | enaddr[4];
948 bus_space_write_4(st, sh, EPIC_LAN2, reg0);
    [all...]
  /src/sys/arch/hpcsh/dev/
psh3lcd.c 71 uint8_t reg0; member in struct:psh3lcd_x0_bcd
142 for (i = 0; psh3lcd_x0_bcd[i].reg0 != 0; i++)
143 if (bcr0 == psh3lcd_x0_bcd[i].reg0 &&
147 if (psh3lcd_x0_bcd[i].reg0 == 0)
182 _reg_write_1(PSH3LCD_BRIGHTNESS_REG0, psh3lcd_x0_bcd[index].reg0);
  /src/sys/arch/shark/shark/
ns87307.c 345 u_char reg0;
356 NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_REG0, reg0 );
366 printf("reg0: %x\n",reg0);
343 u_char reg0; local
  /src/sys/arch/mips/cavium/dev/
octeon_pkovar.h 91 octpko_cmd_word0(int sz1, int sz0, int s1, int reg1, int s0, int reg0,
101 __SHIFTIN(reg0, PKO_CMD_WORD0_REG0) |
  /src/crypto/external/apache2/openssl/dist/crypto/aria/
aria.c 425 register uint32_t reg0, reg1, reg2, reg3; local
440 reg0 = GET_U32_BE(in, 0);
445 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
448 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3);
449 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
453 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3);
454 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
457 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3);
458 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
462 reg0 = rk->u[0] ^ MAKE_U32((uint8_t)(X1[GET_U8_BE(reg0, 0)]), (uint8_t)(X2[GET_U8_BE(reg0, 1)] >> 8), ( (…)
476 register uint32_t reg0, reg1, reg2, reg3; local
609 register uint32_t reg0, reg1, reg2, reg3; local
    [all...]
  /src/crypto/external/bsd/openssl/dist/crypto/aria/
aria.c 474 register uint32_t reg0, reg1, reg2, reg3; local
489 reg0 = GET_U32_BE(in, 0);
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3);
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3);
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3);
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
511 reg0 = rk->u[0] ^ MAKE_U32
541 register uint32_t reg0, reg1, reg2, reg3; local
676 register uint32_t reg0, reg1, reg2, reg3; local
    [all...]
  /src/crypto/external/bsd/openssl.old/dist/crypto/aria/
aria.c 474 register uint32_t reg0, reg1, reg2, reg3; local
489 reg0 = GET_U32_BE(in, 0);
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3);
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3);
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3);
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3);
511 reg0 = rk->u[0] ^ MAKE_U32
541 register uint32_t reg0, reg1, reg2, reg3; local
676 register uint32_t reg0, reg1, reg2, reg3; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_virt.c 54 uint32_t reg0, uint32_t reg1,
65 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
90 pr_err("failed to write reg %x wait reg %x\n", reg0, reg1);
amdgpu_ring.c 392 * @reg0: register to write
401 uint32_t reg0, uint32_t reg1,
404 amdgpu_ring_emit_wreg(ring, reg0, ref);
amdgpu_ring.h 171 uint32_t reg0, uint32_t reg1,
274 uint32_t reg0, uint32_t val0,
amdgpu_virt.h 297 uint32_t reg0, uint32_t rreg1,
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_gmbus.c 684 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
690 gmbus0_source | bus->reg0);
694 gmbus0_source | bus->reg0, 0);
776 bus->adapter.name, bus->reg0 & 0xff);
961 bus->reg0 = pin | GMBUS_RATE_100KHZ;
1002 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
  /src/sys/dev/isa/
wbsio.c 370 uint8_t reg0, reg1, rev; local
384 reg0 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_HM_ADDR_LSB);
390 iobase = (reg1 << 8) | (reg0 & ~0x7);
537 uint8_t reg0, reg1; local
544 reg0 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_GPIO_ADDR_LSB);
546 iobase = (reg1 << 8) | (reg0 & ~0x7);
  /src/sys/arch/hpcmips/vr/
vrc4172gpio.c 161 u_int16_t reg0, reg1; local
163 reg0 = read_2(sc, off);
166 return (reg0|(reg1<<16));
  /src/sys/external/bsd/drm/dist/shared-core/
r128_drv.h 407 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
408 (((reg1) >> 2) << 11) | ((reg0) >> 2))
  /src/sys/external/bsd/drm2/dist/drm/r128/
r128_drv.h 423 #define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \
424 (((reg1) >> 2) << 11) | ((reg0) >> 2))
  /src/sys/arch/arm/rockchip/
rk3588_iomux.c 80 bus_size_t reg0; member in struct:regmaskreg
909 bus_size_t reg0 = rk3588_iomux_regmap[pin].reg0; local
913 if (reg0 != 0) {
915 syscon_write_4(sc->sc_grf, reg0, val);

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