| /src/sys/dev/ic/ |
| rtwvar.h | 118 * Complete outstanding read and/or write ops on [reg0, reg1]
119 * ([reg1, reg0]) before starting new ops on the same region. See
123 rtw_barrier(const struct rtw_regs *r, int reg0, int reg1, int flags)
125 bus_space_barrier(r->r_bt, r->r_bh, MIN(reg0, reg1),
126 MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags);
133 #define RTW_SYNC(regs, reg0, reg1) \
134 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
137 #define RTW_WBW(regs, reg0, reg1) \
138 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE
[all...] |
| smc83c170.c | 898 uint32_t genctl, reg0; local
931 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL);
932 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1);
938 bus_space_write_4(st, sh, EPIC_NVCTL, reg0);
943 reg0 = enaddr[1] << 8 | enaddr[0];
944 bus_space_write_4(st, sh, EPIC_LAN0, reg0);
945 reg0 = enaddr[3] << 8 | enaddr[2];
946 bus_space_write_4(st, sh, EPIC_LAN1, reg0);
947 reg0 = enaddr[5] << 8 | enaddr[4];
948 bus_space_write_4(st, sh, EPIC_LAN2, reg0);
[all...] |
| aic6915.c | 1232 uint32_t reg0, reg1, reg2; local
1234 reg0 = enaddr[5] | (enaddr[4] << 8);
1238 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 0, reg0);
|
| /src/sys/arch/hpcsh/dev/ |
| psh3lcd.c | 71 uint8_t reg0; member in struct:psh3lcd_x0_bcd
142 for (i = 0; psh3lcd_x0_bcd[i].reg0 != 0; i++)
143 if (bcr0 == psh3lcd_x0_bcd[i].reg0 &&
147 if (psh3lcd_x0_bcd[i].reg0 == 0)
182 _reg_write_1(PSH3LCD_BRIGHTNESS_REG0, psh3lcd_x0_bcd[index].reg0);
|
| /src/sys/arch/shark/shark/ |
| ns87307.c | 345 u_char reg0;
356 NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_REG0, reg0 );
366 printf("reg0: %x\n",reg0);
343 u_char reg0; local
|
| /src/sys/arch/mips/cavium/dev/ |
| octeon_pkovar.h | 91 octpko_cmd_word0(int sz1, int sz0, int s1, int reg1, int s0, int reg0,
101 __SHIFTIN(reg0, PKO_CMD_WORD0_REG0) |
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_virt.c | 54 uint32_t reg0, uint32_t reg1,
65 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
90 pr_err("failed to write reg %x wait reg %x\n", reg0, reg1);
|
| amdgpu_ring.c | 392 * @reg0: register to write
401 uint32_t reg0, uint32_t reg1,
404 amdgpu_ring_emit_wreg(ring, reg0, ref);
|
| amdgpu_ring.h | 171 uint32_t reg0, uint32_t reg1,
274 uint32_t reg0, uint32_t val0,
|
| amdgpu_virt.h | 297 uint32_t reg0, uint32_t rreg1,
|
| amdgpu_sdma_v5_0.c | 1181 uint32_t reg0, uint32_t reg1,
1184 amdgpu_ring_emit_wreg(ring, reg0, ref);
1186 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
|
| amdgpu_gfx_v10_0.c | 4793 uint32_t reg0, uint32_t reg1,
4803 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4806 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_gmbus.c | 684 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
690 gmbus0_source | bus->reg0);
694 gmbus0_source | bus->reg0, 0);
776 bus->adapter.name, bus->reg0 & 0xff);
961 bus->reg0 = pin | GMBUS_RATE_100KHZ;
1002 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
|
| /src/sys/dev/isa/ |
| wbsio.c | 370 uint8_t reg0, reg1, rev; local
384 reg0 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_HM_ADDR_LSB);
390 iobase = (reg1 << 8) | (reg0 & ~0x7);
537 uint8_t reg0, reg1; local
544 reg0 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_GPIO_ADDR_LSB);
546 iobase = (reg1 << 8) | (reg0 & ~0x7);
|
| /src/sys/arch/hpcmips/vr/ |
| vrc4172gpio.c | 161 u_int16_t reg0, reg1; local
163 reg0 = read_2(sc, off);
166 return (reg0|(reg1<<16));
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| r128_drv.h | 407 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
408 (((reg1) >> 2) << 11) | ((reg0) >> 2))
|
| mga_drv.h | 344 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
346 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
|
| radeon_drv.h | 1932 #define CP_PACKET1( reg0, reg1 ) \
1933 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
|
| /src/sys/external/bsd/drm2/dist/drm/r128/ |
| r128_drv.h | 423 #define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \
424 (((reg1) >> 2) << 11) | ((reg0) >> 2))
|
| /src/sys/arch/arm/rockchip/ |
| rk3588_iomux.c | 80 bus_size_t reg0; member in struct:regmaskreg
909 bus_size_t reg0 = rk3588_iomux_regmap[pin].reg0; local
913 if (reg0 != 0) {
915 syscon_write_4(sc->sc_grf, reg0, val);
|
| /src/sys/external/bsd/drm2/dist/drm/mga/ |
| mga_drv.h | 342 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
344 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
|
| /src/sys/dev/pci/ |
| gffb.c | 786 uint8_t reg0, reg1; local
791 reg0 = gffb_read_crtc(sc, 0, 0x1a) & 0x3f;
795 reg0 |= 0xc0;
799 gffb_write_crtc(sc, 0, 0x1a, reg0);
|
| /src/sys/arch/mips/mips/ |
| mipsX_subr.S | 2136 1: _MTC0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
2152 _MTC0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
2172 _MTC0 t0, MIPS_COP_0_TLB_LO0 # init low reg0.
|
| /src/sys/dev/usb/ |
| if_urtwn.c | 4575 uint32_t reg0, reg1, reg2; local
4589 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
4660 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 534 u32 reg0; member in struct:intel_gmbus
|
